Datasheet

ADS1251
3
SBAS184D
www.ti.com
ELECTRICAL CHARACTERISTICS (Cont.)
All specifications at T
MIN
to T
MAX
, V
DD
= +5V, CLK = 8MHz, and V
REF
= 4.096, unless otherwise specified.
ADS1251U
PARAMETER CONDITIONS MIN TYP MAX UNITS
VOLTAGE REFERENCE
V
REF
0.5 4.096 V
DD
V
Load Current 32 µA
DIGITAL INPUT/OUTPUT
Logic Family CMOS
Logic Level: V
IH
+4.0 +V
DD
+ 0.3 V
V
IL
–0.3 +0.8 V
V
OH
I
OH
= –500µA +4.5 V
V
OL
I
OL
= 500µA 0.4 V
Input (SCLK, CLK) Hysteresis 0.6 V
Data Format
Offset Binary Two’s Complement
POWER-SUPPLY REQUIREMENTS
Operation +4.75 +5 +5.25 VDC
Quiescent Current V
DD
= +5VDC 1.5 2 mA
Operating Power 7.5 10 mW
Power-Down Current 0.4 1 µA
TEMPERATURE RANGE
Operating –40 +85 °C
Storage –60 +100 °C
PIN CONFIGURATION
Top View SO
PIN DESCRIPTIONS
PIN NAME PIN DESCRIPTION
1+V
IN
Analog Input: Positive Input of the Differen-
tial Analog Input
2–V
IN
Analog Input: Negative Input of the Differ-
ential Analog Input.
3+V
DD
Input: Power-Supply Voltage, +5V
4 CLK Digital Input: Device System Clock. The
system clock is in the form of a CMOS-
compatible clock. This is a Schmitt-Trigger
input.
5
DOUT/DRDY
Digital Output: Serial Data Output/Data
Ready. This output indicates that a new
output word is available from the ADS1251
data output register. The serial data is
clocked out of the serial data output shift
register using SCLK.
6 SCLK Digital Input: Serial Clock. The serial clock
is in the form of a CMOS-compatible clock.
The serial clock operates independently
from the system clock, therefore, it is pos-
sible to run SCLK at a higher frequency
than CLK. The normal state of SCLK is
LOW. Holding SCLK HIGH will either ini-
tiate a modulator reset for synchronizing
multiple converters or enter power-down
mode. This is a Schmitt-Trigger input.
7 GND Input: Ground
8V
REF
Analog Input: Reference Voltage Input
+V
IN
ADS1251U
GND
–V
IN
V
REF
+V
DD
SCLK
DOUT/DRDY
CLK
1
2
3
4
8
7
6
5