Datasheet

ADS1251
12
SBAS184D
www.ti.com
POWER-DOWN MODE
The normal state of SCLK is LOW; however, by holding
SCLK HIGH, the ADS1251 will enter power-down mode. This
is accomplished by holding SCLK HIGH for at least 20
consecutive DOUT/DRDY
periods (see Figure 14). After the
ADS1251 circuitry detects that SCLK has been held HIGH for
four consecutive DOUT/DRDY
cycles, the DOUT/DRDY pin
pulses LOW for one CLK cycle and then is held HIGH, and
the modulator is held in a reset state. If SCLK is held HIGH
for an additional 16 DOUT/DRDY
periods, the ADS1251
enters power-down mode. The part will be released from
power-down mode on the falling edge of SCLK. It is impor-
tant to note that the DOUT/DRDY
pin is held HIGH after four
DOUT/DRDY
cycles, but power-down mode is not entered
for an additional 16 DOUT/DRDY
periods. The first
DOUT/DRDY
pulse after the falling edge of SCLK occurs at
t
16
and indicates valid data. Subsequent DOUT/DRDY pulses
will occur normally.
SERIAL INTERFACE
The ADS1251 includes a simple serial interface which can be
connected to microcontrollers and digital signal processors in
a variety of ways. Communications with the ADS1251 can
commence on the first detection of the DOUT/DRDY
pulse
after power up.
It is important to note that the data from the ADS1251 is a
24-bit result transmitted MSB-first in Offset Binary Twos
Complement format, as shown in Table III.
The data must be clocked out before the ADS1251 enters
DRDY mode to ensure reception of valid data, as described
in the
DOUT/DRDY
section of this data sheet.
TABLE III. ADS1251 Data Format (Offset Binary Twos
Complement).
DIFFERENTIAL VOLTAGE INPUT DIGITAL OUTPUT (HEX)
+Full-Scale 7FFFFF
H
Zero 000000
H
–Full-Scale 800000
H
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
DRDY
Conversion Cycle 384 • CLK ns
DRDY
Mode
DRDY
Mode 36 • CLK ns
DOUT Mode DOUT Mode 348 • CLK ns
t
1
DOR Write Time 6 • CLK ns
t
2
DOUT/DRDY
LOW Time 6 • CLK ns
t
3
DOUT/DRDY
HIGH Time (Prior to Data Out) 6 • CLK ns
t
4
DOUT/DRDY
HIGH Time (Prior to Data Ready) 24 • CLK ns
t
5
Rising Edge of CLK to Falling Edge of
DOUT/DRDY
30 ns
t
6
End of
DRDY
Mode to Rising Edge of First SCLK 30 ns
t
7
End of
DRDY
Mode to Data Valid (Propagation Delay) 30 ns
t
8
Falling Edge of SCLK to Data Valid (Hold Time) 5 ns
t
9
Falling Edge of SCLK to Next Data Out Valid (Propagation Delay) 30 ns
t
10
SCLK Setup Time for Synchronization or Power Down 30 ns
t
11
DOUT/DRDY
Pulse for Synchronization or Power Down 3 • CLK ns
t
12
Rising Edge of SCLK Until Start of Synchronization 1537 • CLK 7679 • CLK ns
t
13
Synchronization Time 0.5 • CLK 6143.5 • CLK ns
t
14
Falling Edge of CLK (After SCLK Goes LOW) Until Start of
DRDY
Mode 2042.5 • CLK ns
t
15
Rising Edge of SCLK Until Start of Power Down 7681 • CLK ns
t
16
Falling Edge of CLK (After SCLK Goes LOW) Until Start of
DRDY
Mode 2318.5 • CLK ns
t
17
Falling Edge of Last
DOUT/DRDY
to Start of Power Down 6144.5 • CLK ns
TABLE II. Digital Timing.
FIGURE 11. DOUT/DRDY Partitioning.
DATA
DRDY Mode
DOUT ModeDOUT Mode
DATA DATA
t
4
t
2
t
3
t
1
DRDY Mode
DOUT/DRDY