Datasheet

16
ADS1250
®
Method 3: Three-Wire Interface
The third method of receiving data uses a simple three-wire
interface (SCLK, DOUT, and DRDY). The main difference
from method 1 is that CS is tied LOW, therefore, the DOUT
pin is always driving the bus. The DRDY line will pulse
LOW after the DOR is updated. Since CS is tied LOW (the
DOUT pin is enabled for output), the level dictated by the
MSB of the data output register would be driven on the bus.
The processor would provide 20 (or 24) SCLKs to read the
contents of the DOR. The data bits in the DOR are shifted
out on the DOUT pin after the falling edge of SCLK. If more
than 20 bits of data are read, the data is 0 padded. Since CS
is tied LOW, the bus will be driven to the state of the last bit
that was shifted out of the DOR. The timing for the data
transfer is shown in Figure 20 (see Table III). A simple
three-wire interface using this method is shown in Figure 21.
The P1.0 output from the 8xC51 is a free-running clock.
Figure 22 shows a five-wire interface using DSYNC. The
communication with the ADS1250 is the same as described
in Method 1. Figure 23 shows a full interface using DSYNC,
G1, and G0. The communication with ADS1250 is the same
as described in Method 1.
FIGURE 20. Method 3: Two-Wire Interface (CS tied LOW).
12 19
OUT
MSB
DOUT
SCLK
DRDY
CLK
20 21 22 23 24
t
5
t
9
t
8
t
2
t
10
t
11
OUT
LSB
FIGURE 21. Three-Wire Interface to an 8xC51 (CS tied LOW).
DV
DD
DV
DD
8xC51
P1.0 / T2
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
P3.0
P3.1
P3.2 / INT0
P3.3
P3.4
P3.5
P3.6
P3.7
XTAL2
XTAL1
V
SS
V
CC
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
EA
ALE
PSEN
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
DGND
C1
XTAL
C2
+V
IN
–V
IN
AGND
+V
S
V
REF
DSYNC
+V
D
DGND
DGND
G1
G0
CS
DRDY
CLK
SCLK
DOUT
DV
DD
V
REF
Circuit
AGND
AV
DD
DGND
DGND
ADS1250