Datasheet

15
®
ADS1250
19
OUT
LSB
DOUT
SCLK
CS
DRDY
CLK
20 21 22 23 24
t
5
t
6
t
12
t
7
12
OUT
MSB
t
9
t
10
t
11
t
8
FIGURE 18. Method 2: Four-Wire Interface Using a Free-Running SCLK.
Method 2: Four-Wire Interface
The second method of receiving data also uses a simple
four-wire interface (CS, SCLK, DOUT, and DRDY). The
main difference from method 1 is that SCLK is a free-
running clock. The DRDY line will pulse LOW for the time
defined by t
2
after the DOR is updated. The processor would
then take CS LOW to select the device for communication.
The recommended method of using CS is to take CS LOW
on the falling edge of SCLK. The only timing constraint of
CS is that the setup time (t
9
) for the data must be met before
the rising edge of SCLK. Once CS is taken LOW, the DOUT
would be driven to the level dictated by the MSB of the data
output register. CS would be held low for 20 (or 24) SCLKs
to read the contents of the DOR. The data bits in the DOR
are shifted out on the DOUT pin after the falling edge of
SCLK. If CS is held low for more than 20 SCLKs, the data
would be 0 padded. Taking CS HIGH will take DOUT to a
high-impedance state. The timing for the data transfer is
shown in Figure 18 (see Table III). A simple four-wire
interface is shown in Figure 19. The P1.0 output from the
8xC51 is a free-running clock.
FIGURE 19. Four-Wire Interface to an 8xC51 (Free-Running SCLK).
DV
DD
DV
DD
8xC51
P1.0 / T2
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
P3.0
P3.1
P3.2 / INT0
P3.3
P3.4
P3.5
P3.6
P3.7
XTAL2
XTAL1
V
SS
V
CC
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
EA
ALE
PSEN
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
DGND
C1
XTAL
C2
+V
IN
–V
IN
AGND
+V
S
V
REF
DSYNC
+V
D
DGND
DGND
G1
G0
CS
DRDY
CLK
SCLK
DOUT
DV
DD
V
REF
Circuit
AGND
AV
DD
DGND
DGND
ADS1250