Datasheet

12
ADS1250
®
FIGURE 11. DSYNC to CLK Timing for Synchronizing
Multiple ADS1250s.
t
13
t
14
CLK
DSYNC
FIGURE 12. Exactly Synchronizing Multiple ADS1250s to an Asynchronous DSYNC Signal.
DSYNC
CLK
DGND
ADS1250
DOUT
SCLK
DV
DD
D
CLK
1/2 74AHC74
1/6 74AHC04
Q
Q
DSYNC
CLK
DGND
ADS1250
DOUT
SCLK
DV
DD
DSYNC
CLK
DGND
ADS1250
DOUT
SCLK
DV
DD
Asynchronous
DSYNC
Strobe
DGND
DV
DD
OSC
TABLE III. Digital Timing.
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
1
DOR Write Time (Using CS) 6 • CLK ns
t
2
DRDY LOW Time 6 • CLK ns
t
3
DOR Write Time (CS HIGH) 6 • CLK ns
t
4
DRDY HIGH Time 6 • CLK ns
t
5
Rising Edge of CLK to Falling Edge of DRDY 30 ns
t
6
Falling Edge of DRDY to Falling Edge of CS 30 ns
t
7
Falling Edge of CS to Rising Edge of DRDY 6 • CLK ns
t
8
Falling Edge of CS to Rising Edge of SCLK or
Falling Edge of DRDY to Rising Edge of SCLK if CS is Tied LOW 30 ns
t
9
Falling Edge of CS to DOUT Valid or
Falling Edge of DRDY to DOUT Valid if CS is Tied LOW (Setup Time) 30 ns
t
10
Falling Edge of SCLK to DOUT Valid (Hold Time) 5 ns
t
11
Falling Edge of SCLK to Next DOUT Valid (Setup Time) 30 ns
t
12
Rising Edge of CS to DOUT High Impedance 30 ns
t
13
DSYNC Pulse Width 100 ns
t
14
Falling Edge of CLK to Falling Edge of DSYNC – 5 ns
CLK
2
DSYNC
The DSYNC signal can be used is two ways. First, DSYNC
can be used to synchronize multiple converters. This is done
by applying a negative-going pulse on DSYNC. The nega-
tive pulse resets the current modulator count to zero and
places it in a hold state. The modulator is released from the
hold state and synchronization occurs on the rising edge of
DSYNC. DSYNC does not reset the internal data to zero.
Synchronization assumes that each ADS1250 is driven from
the same system clock. If the DSYNC pulse is completely
asynchronous to the master clock, some ADS1250s may
start-up one CLK clock cycle before the others.
Therefore, the output data will be synchronized, but only to
within one CLK clock cycle. To ensure exact synchroniza-
tion to the same CLK clock edge, the timing relationship
between the DSYNC and CLK signals must be observed, as
shown in Figure 11 and Table III. Figure 12 shows a simple
circuit which can be used to clock multiple ADS1250s from
one ADS1250, as well as to ensure that an asynchronous
DSYNC signal will exactly synchronize all the converters.
The second use of DSYNC is to reset the modulator count
to zero in order to obtain valid data as quickly as possible.
For example, if the analog input signal is changed signifi-
cantly on the ADS1250, the current conversion cycle will be
a mix of the old data and the new data. Five conversions are
needed for the digital filter to settle. Therefore, the sixth
conversion will be valid data. However, if the analog input
signal is changed and then DSYNC is used to reset the
modulator count, the modulator data at the end of the current
conversion cycle will be entirely from the new signal. After
four additional conversion cycles, the output data will be
completely valid. Note that the conversion cycle in which
DSYNC is used will be slightly longer than normal. Its
length will depend on when DSYNC was set.