Datasheet

10
ADS1250
®
The digital output rate, or data rate, scales directly with the
system CLK frequency. This allows the data output rate to
be changed over a very wide range (five orders of magni-
tude) by changing the system CLK frequency. However, it
is important to note that the –3dB point of the filter is 0.216
times the data output rate. Therefore, the data output rate
should allow for sufficient margin to prevent attenuation of
the signal of interest.
Since the conversion result is essentially an average, the data
output rate determines the location of the resulting notches
in the digital filter (see Figure 3). Note that the first notch is
located at the data output rate frequency, and subsequent
notches are located at integer multiples of the data output
rate to allow for rejection of not only the fundamental
frequency, but also harmonic frequencies. In this manner,
the data output rate can be used to set specific notch
frequencies in the digital filter response.
For example, if rejection of the power line frequency is
desired, the data output rate can simply be set to the power
line frequency. For 50Hz rejection, the system CLK fre-
quency should be 19.200kHz; this will set the data output
rate to 50Hz (see Table II and Figure 4). For 60Hz rejection,
the system CLK frequency should be 23.040kHz; this will
set the data output rate to 60Hz (see Table II and Figure 5).
If both 50Hz and 60Hz rejection is required, then the system
CLK should be 3.840kHz; this will set the data output rate
to 10Hz and reject both 50Hz and 60Hz (See Table II and
Figure 6).
FIGURE 3. Normalized Digital Filter Response. FIGURE 4. Digital Filter Response (50Hz).
NORMALIZED DIGITAL FILTER RESPONSE
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200
123456789100
Frequency (Hz)
Gain (dB)
DIGITAL FILTER RESPONSE
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200
50 100 150 200 250 3000
Frequency (Hz)
Gain (dB)
There is an additional benefit in using a lower data output
rate. It will provide better rejection of signals in the fre-
quency band of interest. For example, with a 50Hz data
output rate, a significant signal at 75Hz may alias back into
the passband at 25Hz. This is due to the fact that rejection at
75Hz may only be 66dB in the stopband (frequencies higher
than the first notch frequency), as shown in Figure 4.
However, setting the data output rate to 10Hz will provide
135dB rejection at 75Hz (see Figure 6). A similar benefit is
gained at frequencies near the data output rate (see Figures
7, 8, 9, and 10). If a slower data output rate does not meet
the system requirements, the analog front end can be de-
signed to provide the needed attenuation to prevent aliasing.
Additionally the data output rate may be increased and
additional digital filtering may be done in the processor or
controller.
CONTROL LOGIC
The control logic is used for communications and control of
the ADS1250.
Power-Up Sequence
Prior to power-up, all digital and analog input pins must be
LOW. At the time of power-up, these signal inputs can be
biased to a voltage other than 0V, however, they should
never exceed +V
S
or +V
D
.
Once the ADS1250 powers up, the DRDY line will pulse
LOW on the first conversion. This data will not be valid. The
sixth pulse of DRDY will be valid data from the analog input
signal.