Datasheet

DVDD
START
RESET
CS
DRDY
SCLK
00
Conversionresult
forchannel1
Power-upsequence ADCinitialsetup
ADCisputtosleep
afterasingleconversion.
Dataareretrievedwhen
ADCissleeping.
Initialsetting:
AIN0isthepositivechannel,
AIN1isthenegativechannel,
internalreferenceselected,
PGAgain=32,
datarate=2kSPS,
VBIASisconnectedtothe
negativepins,AIN1andAIN3.
ADCenters
power-saving
sleepmode
01 02 03
WREG
DIN
DOUT
t
DRDY
(0.575ms)
NOP
16ms
(1)
ADS1246
ADS1247
ADS1248
SBAS426G –AUGUST 2008–REVISED OCTOBER 2011 www.ti.com
Sleep Mode Example
be changed by performing a block write operation on
the first four registers of the device. After performing
This second example deals with performing one
the block write operation, the START pin can be
conversion after power-up and then entering into the
taken low. The device enters the power-saving sleep
power-saving sleep mode. In this example, a sensor
mode as soon as DRDY goes low 0.575ms after
is connected to input channels AIN0 and AIN1.
writing into the SYS0 register. The conversion result
Commands to set up the devices must occur at least
can be retrieved even after the device enters sleep
2
16
system clock cycles after powering up the
mode by sending 16 SPI clock pulses.
devices. The ADC operates at a data rate of 2kSPS.
The PGA gain is set to 32 for both sensors. VBIAS is
connected to the negative terminal of both the
sensors (that is, channel AIN1). All these settings can
(1) For f
OSC
= 4.096MHz.
Figure 84. SPI Communication Sequence for Entering Sleep Mode After a Conversion
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