Datasheet

ADS1246
ADS1247
ADS1248
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SBAS426G AUGUST 2008REVISED OCTOBER 2011
ADS1246 DETAILED REGISTER DEFINITIONS (continued)
VBIASBias Voltage Register. This register enables a bias voltage on the analog inputs.
VBIAS - ADDRESS 01h RESET VALUE = 00h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0 0 0 0 0 0 VBIAS1 VBIAS0
Bits 7:2 These bits must always be set to '000000'.
Bits 1:0 VBIAS1:0
These bits apply a bias voltage of midsupply (AVDD + AVSS)/2 to the selected analog input. Bit 0
is for AIN0, and bit 1 is for AIN1.
0 = Bias voltage not enabled (default)
1 = Bias voltage is applied to the analog input
MUXMultiplexer Control Register.
MUX - ADDRESS 02h RESET VALUE = x0h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CLKSTAT 0 0 0 0 MUXCAL2 MUXCAL1 MUXCAL0
Bit 7 CLKSTAT
This bit is read-only and indicates whether the internal or external oscillator is being used.
0 = Internal oscillator in use
1 = External oscillator in use
Bits 6:3 These bits must always be set to '0000'.
Bits 2:0 MUXCAL2:0
These bits are used to select a system monitor. The MUXCAL selection supercedes selections
from the VBIAS register.
000 = Normal operation (default)
001 = Offset calibration. The analog inputs are disconnected and AINP and AINN are internally
connected to midsupply (AVDD + AVSS)/2.
010 = Gain calibration. The analog inputs are connected to the voltage reference.
011 = Temperature measurement. The inputs are connected to a diode circuit that produces a
voltage proportional to the ambient temperature of the device..
Table 19 lists the ADC input connection and PGA settings for each MUXCAL setting. The PGA setting reverts to
the original SYS0 register setting when MUXCAL is taken back to normal operation or offset measurement.
Table 19. MUXCAL Settings
MUXCAL[2:0] PGA GAIN SETTING ADC INPUT
000 Set by SYS0 register Normal operation
001 Set by SYS0 register Offset calibration: inputs shorted to midsupply (AVDD + AVSS)/2
010 Forced to 1 Gain calibration: V
REFP
V
REFN
(full-scale)
011 Forced to 1 Temperature measurement diode
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