Datasheet

SCLK
DIN
1
1
D[23] D[22]D[23]D[22] D[21]
NOP NOP
D[2] D[1] D[0] D[0]
2
2
3 22 23 24
24
DOUT/
(1)
DRDY
DRDY
SCLK
DIN
1
1
D[23] D[22]D[23]D[22] D[21]
NOP NOP NOP
D[2] D[1] D[0] D[0]
2
2
3 22 23 24 1 2 8
24
DOUT/
(1)
DRDY
DRDY
SCLK
DOUT/
(1)
DRDY
DIN NOP
1
reg[7] reg[1] reg[0]
2 1 2 7 87 8
NOP
ADS1246
ADS1247
ADS1248
www.ti.com SBAS426G –AUGUST 2008–REVISED OCTOBER 2011
(1) CS tied low.
Figure 70. Data Retrieval with the DRDY MODE Bit = 1 (Enabled)
(1) DRDY MODE bit enabled, CS tied low.
Figure 71. DOUT/DRDY Forced High After Retrieving the Conversion Result
(1) DRDY MODE bit enabled, CS tied low.
Figure 72. DOUT/DRDY Forced High After Reading Register Data
The DRDY MODE bit modifies only the DOUT/DRDY
SPI Communication During Sleep Mode
pin functionality. The DRDY pin functionality remains
unaffected.
When the START pin is low or the device is in sleep
mode, only the RDATA, RDATAC, SDATAC,
SPI Reset
WAKEUP, and NOP commands can be issued. The
RDATA command can be used to repeatedly read the
SPI communication can be reset in several ways. In
last conversion result during sleep mode. Other
order to reset the SPI interface (without resetting the
commands do not function because the internal clock
registers or the digital filter), the CS pin can be pulled
is shut down to save power during sleep mode.
high. Taking the RESET pin low causes the SPI
interface to be reset along with all the other digital
functions. In this case, the registers and the
conversion are reset.
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