Datasheet

SCLK
D[23]
1 2 22 1 2 823 243
D[22] D[21] D[2] D[1] D[0]
DOUT/
(1)
DRDY
DRDY
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SCLK DOUT/DRDY
The serial clock signal. SCLK provides the clock for This pin has two modes: data out (DOUT) only, or
serial communication. It is a Schmitt-trigger input, but data out (DOUT) combined with data ready (DRDY).
it is highly recommended that SCLK be kept as clean The DRDY MODE bit determines the function of this
as possible to prevent glitches from inadvertently pin. In either mode, the DOUT/DRDY pin goes to a
shifting the data. Data are shifted into DIN on the high-impedance state when CS is taken high.
falling edge of SCLK and shifted out of DOUT on the
When the DRDY MODE bit is set to '0', this pin
rising edge of SCLK.
functions as DOUT only. Data are clocked out at
DIN rising edge of SCLK, MSB first (see Figure 69).
The data input pin. DIN is used along with SCLK to
When the DRDY MODE bit is set to '1', this pin
send data to the device. Data on DIN are shifted into
functions as both DOUT and DRDY. Data are shifted
the device on the falling edge of SCLK.
out from this pin, MSB first, at the rising edge of
The communication of this device is full-duplex in SCLK. This combined pin allows for the same control
nature. The device monitors commands shifted in but with fewer pins.
even when data are being shifted out. Data that are
When the DRDY MODE bit is enabled and a new
present in the output shift register are shifted out
conversion is complete, DOUT/DRDY goes low if it is
when sending in a command. Therefore, it is
high. If it is already low, then DOUT/DRDY goes high
important to make sure that whatever is being sent on
and then goes low (see Figure 70). Similar to the
the DIN pin is valid when shifting out data. When no
DRDY pin, a falling edge on the DOUT/DRDY pin
command is to be sent to the device when reading
signals that a new conversion result is ready. After
out data, the NOP command should be sent on DIN.
DOUT/DRDY goes low, the data can be clocked out
DRDY by providing 24 SCLKs. In order to force
The data ready pin. The DRDY pin goes low to DOUT/DRDY high (so that DOUT/DRDY can be
indicate a new conversion is complete, and the polled for a '0' instead of waiting for a falling edge), a
conversion result is stored in the conversion result no operation command (NOP) or any other command
buffer. The SPI clock must be low in a short time that does not load the data output register can be
frame around the DRDY low transition (see Figure 2) sent after reading out the data. Because SCLKs can
so that the conversion result is loaded into both the only be sent in multiples of eight, a NOP can be sent
result buffer and the output shift register. Therefore, to force DOUT/DRDY high if no other command is
no commands should be issued during this time pending. The DOUT/DRDY pin goes high after the
frame if the conversion result is to be read out later. first rising edge of SCLK after reading the conversion
This constraint applies only when CS is asserted. result completely (see Figure 71). The same condition
When CS is not asserted, SPI communication with also applies after an RREG command. After all the
other devices on the SPI bus does not affect loading register bits have been read out, the rising edge of
of the conversion result. After the DRDY pin goes SCLK forces DOUT/DRDY high. Figure 72 illustrates
low, it is forced high on the first falling edge of SCLK an example where sending four NOP commands after
(so that the DRDY pin can be polled for '0' instead of an RREG command forces the DOUT/DRDY pin
waiting for a falling edge). If the DRDY pin is not high.
taken high after it falls low, a short high pulse is
created on it to indicate the next data are ready.
(1) CS tied low.
Figure 69. Data Retrieval with the DRDY MODE Bit = 0 (Disabled)
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