Datasheet

ADS1246
ADS1247
ADS1248
www.ti.com SBAS426G –AUGUST 2008–REVISED OCTOBER 2011
Table 16. Data Conversion Time
FIRST DATA CONVERSION TIME AFTER FILTER RESET
HARDWARE RESET, RESET
COMMAND, START PIN HIGH,
WAKEUP COMMAND, VBIAS, SECOND AND SUBSEQUENT
SYNC COMMAND, MUX0 MUX1, or SYS0 REGISTER CONVERSION TIME AFTER
REGISTER WRITE WRITE FILTER RESET
NO. OF NO. OF NO. OF
NOMINAL EXACT DATA SYSTEM SYSTEM SYSTEM
DATA RATE RATE CLOCK CLOCK CLOCK
(SPS) (SPS) (ms)
(1)
CYCLES (ms)
(1)
CYCLES (ms) CYCLES
5 5.019 199.258 816160 200.26 820265 199.250 816128
10 10.038 99.633 408096 100.635 412201 99.625 408064
20 20.075 49.820 204064 50.822 208169 49.812 204032
40 40.151 24.92 102072 25.172 103106 24.906 102016
80 80.301 12.467 51064 12.719 52098 12.453 51008
160 160.602 6.240 25560 6.492 26594 6.226 25504
320 321.608 3.124 12796 3.25 13314 3.109 12736
640 643.216 1.569 6428 1.695 6946 1.554 6368
1000 1000 1.014 4156 1.141 4674 1 4096
2000 2000 0.514 2108 0.578 2370 0.5 2048
(1) For f
OSC
= 4.096MHz.
command and the RDATA command. These
Data Format
limitations are explained in detail in the SPI
Commands section of this data sheet. For the basic
The ADS1246/7/8 output 24 bits of data in binary
serial interface timing characteristics, see Figure 1
twos complement format. The least significant bit
and Figure 2 of this datasheet.
(LSB) has a weight of (V
REF
/PGA)/(2
23
– 1). The
positive full-scale input produces an output code of
CS
7FFFFFh and the negative full-scale input produces
The chip select pin (active low). The CS pin activates
an output code of 800000h. The output clips at these
SPI communication. CS must be low before data
codes for signals exceeding full-scale. Table 17
transactions and must stay low for the entire SPI
summarizes the ideal output codes for different input
communication period. When CS is high, the
signals.
DOUT/DRDY pin enters a high-impedance state.
Therefore, reading and writing to the serial interface
Table 17. Ideal Output Code vs Input Signal
are ignored and the serial interface is reset. DRDY
pin operation is independent of CS.
INPUT SIGNAL, V
IN
(AIN
P
– AIN
N
) IDEAL OUTPUT CODE
Taking CS high deactivates only the SPI
≥ +V
REF
/PGA 7FFFFFh
communication with the device. Data conversion
(+V
REF
/PGA)/(2
23
– 1) 000001h
continues and the DRDY signal can be monitored to
check if a new conversion result is ready. A master
0 000000h
device monitoring the DRDY signal can select the
(–V
REF
/PGA)/(2
23
– 1) FFFFFFh
appropriate slave device by pulling the CS pin low.
≤ –(V
REF
/PGA) × (2
23
/2
23
– 1) 800000h
The ADS1246/7/8 implement a timeout function for all
1. Excludes effects of noise, linearity, offset, and
listed commands in the event that data is corrupted
gain errors.
and chip select is permanently tied low. However, it is
important in systems where chip select is tied low
Digital Interface
permanently that register writes always be fully
completed in 8 bit increments. The SCLK line should
The ADS1246/7/8 provide a standard SPI serial
also be kept clean and situations should be avoided
communication interface plus a data ready signal
where noise on the SCLK line could cause the device
(DRDY). Communication is full-duplex with the
to interpret the transient as a false SCLK. In systems
exception of a few limitations in regards to the RREG
where such events are likely to occur, it is
recommended that chip select be used to frame
communications to the device.
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