Datasheet

ADS1246
ADS1247
ADS1248
SBAS426G –AUGUST 2008–REVISED OCTOBER 2011 www.ti.com
With the START pin held high, the ADC converts the an overload state can cause the chopper to become
selected input channels continuously. This unstable. This instability results in slow settling time.
configuration continues until the START pin is taken To prevent this slow settling, always change the PGA
low. The START pin can also be used to perform the setting or MUX setting to a non-overloaded state
synchronized measurement for the multi-channel before changing the data rate.
applications by pulsing the START pin.
Single-Cycle Settling
RESET
The ADS1246/7/8 are capable of single-cycle settling
When the RESET pin goes low, the device is
across all gains and data rates. However, to achieve
immediately reset. All the registers are restored to
single-cycle settling at 2kSPS, special care must be
default values. The device stays in reset mode as
taken with respect to the interface. When operating at
long as the RESET pin stays low. When it goes high,
2kSPS, the SPI data SCLK period must not exceed
the ADC comes out of reset mode and is able to
520ns, and the time between the beginning of a byte
convert data. After the RESET pin goes high, and
and the beginning of a subsequent byte must not
when the system clock frequency is 4.096MHz, the
exceed 4.2µs. Additionally, when performing multiple
digital filter and the registers are held in a reset state
individual write commands to the first four registers,
for 0.6ms when f
OSC
= 4.096MHz. Therefore, valid
wait at least 64 oscillator clocks before initiating
SPI communication can only be resumed 0.6ms after
another write command.
the RESET pin goes high; see Figure 4. When the
RESET pin goes low, the clock selection is reset to
Digital Filter Reset Operation
the internal oscillator.
Apart from the RESET command and the RESET pin,
Channel Cycling and Overload Recovery
the digital filter is reset automatically when either a
write operation to the MUX0, VBIAS, MUX1, or SYS0
When cycling through channels, care must be taken
registers is performed, when a SYNC command is
when configuring the ADS1246/7/8 to ensure that
issued, or the START pin is taken high.
settling occurs within one cycle. For setups that
simply cycle through MUX channels, but do not
The filter is reset two system clocks after the last bit
change PGA and data rate settings, simply changing
of the SYNC command is sent. The reset pulse
the MUX0 register is sufficient. However, when
created internally lasts for two multiplier clock cycles.
changing PGA and data rate settings it is important to
If any write operation takes place in the MUX0
ensure that an overloaded condition cannot occur
register, the filter is reset regardless of whether the
during the transmission. When configuration data are
value changed or not. Internally, the filter pulse lasts
transferred to the ADS1246/7/8, new settings become
for two system clock periods. If any write activity
active at the end of each byte sent. Therefore, a brief
takes place in the VBIAS, MUX1, or SYS0 registers,
overload condition can occur during the transmission
the filter is reset as well, regardless of whether the
of configuration data after the completion of the
value changed or not. The reset pulse lasts for 32
MUX0 byte and before completion of the SYS0 byte.
modulator clocks after the write operation. If there are
This temporary overload can result in intermittent
multiple write operations, the resulting reset pulse
incorrect readings. To ensure that an overload does
may be viewed as the ANDed result of the different
not occur, it may be necessary to split the
active low pulses created individually by each action.
communication into two separate communications
Table 16 shows the conversion time after a filter
allowing the change of the SYS0 register before the
reset. Note that this time depends on the operation
change of the MUX0 register.
initiating the reset. Also, the first conversion after a
In the event of an overloaded state, care must also
filter reset has a slightly different time than the
be taken to ensure single cycle settling into the next
second and subsequent conversions.
cycle. Because the ADS1246/7/8 implement a
chopper-stabilized PGA, changing data rates during
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