Datasheet

Converting
START
DOUT/DRDY
SCLK
DRDY
ADS1246/47/48
Status
Shutdown
1 2 3 24
t
CONV
t
START
Converting Converting Converting Converting
START
DOUT/DRDY
ADS1246/47/48
Status
DataReady DataReady DataReady
ADS1246
ADS1247
ADS1248
www.ti.com SBAS426G –AUGUST 2008–REVISED OCTOBER 2011
ADC CONTROL configuration registers. The device stays shut down
until the START pin is once again taken high to begin
ADC Conversion Control a new conversion. When the START pin is taken
back high again, the decimation filter is held in a
The START pin provides easy and precise control of
reset state for 32 modulator clock cycles internally to
conversions. Pulse the START pin high to begin a
allow the analog circuits to settle.
conversion, as shown in Figure 67 and Table 15. The
conversion completion is indicated by the The ADS1246/7/8 can be configured to convert
DOUT/DRDY pin going low. When the conversion continuously by holding the START pin high, as
completes, the ADS1246/7/8 automatically shuts shown in Figure 68.
down to save power. During shutdown, the
conversion result can be retrieved; however, START
must be taken high before communicating with the
Figure 67. Timing for Single Conversion Using START Pin
Table 15. START Pin Conversion Times for Figure 67
SYMBOL DESCRIPTION DATA RATE (SPS) VALUE UNIT
5 200.295 ms
10 100.644 ms
20 50.825 ms
40 25.169 ms
80 12.716 ms
Time from START pulse to DRDY and
t
CONV
DOUT/DRDY going low
160 6.489 ms
320 3.247 ms
640 1.692 ms
1000 1.138 ms
2000 0.575 ms
NOTE: SCLK held low in this example.
Figure 68. Timing for Conversion with START Pin High
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