Datasheet

()
(V )(Gain)
IN
2
AVSS+0.1V +
£ V
CMI
£
()
(V )(Gain)
IN
2
AVDD 0.1V- -
ADC
A1
454W
454W
7.5pF
A2
7.5pF
7.5pF
7.5pF
R
R
C
AIN
P
AIN
N
ADS1246
ADS1247
ADS1248
SBAS426G –AUGUST 2008–REVISED OCTOBER 2011 www.ti.com
LOW-NOISE PGA MODULATOR
The ADS1246/7/8 feature a low-drift, low-noise, high A third-order modulator is used in the ADS1246/7/8.
input impedance programmable gain amplifier (PGA). The modulator converts the analog input voltage into
The PGA can be set to gain of 1, 2, 4, 8, 16, 32, 64, a pulse code modulated (PCM) data stream. To save
or 128 by register SYS0. A simplified diagram of the power, the modulator clock runs from 32kHz up to
PGA is shown in Figure 53. 512kHz for different data rates, as shown in Table 8.
The PGA consists of two chopper-stabilized
Table 8. Modulator Clock Frequency for Different
amplifiers (A1 and A2) and a resistor feedback
Data Rates
network that sets the gain of the PGA. The PGA input
DATA RATE f
MOD
is equipped with an electromagnetic interference
(SPS) (kHz)
(EMI) filter, as shown in Figure 53. Note that as with
5, 10, 20 32
any PGA, it is necessary to ensure that the input
voltage stays within the specified common-mode 40, 80, 160 128
input range specified in the Electrical Characteristics.
320, 640, 1000 256
The common-mode input (V
CMI
) must be within the
2000 512
range shown in Equation 4:
DIGITAL FILTER
(4)
The ADS1246/7/8 use linear-phase finite impulse
response (FIR) digital filters that can be adjusted for
different output data rates. The digital filter always
settles in a single cycle.
Table 9 shows the exact data rates when an external
oscillator equal to 4.096MHz is used. Also shown is
the signal –3dB bandwidth, and the 50Hz and 60Hz
attenuation. For good 50Hz or 60Hz rejection, use a
data rate of 20SPS or slower.
The frequency responses of the digital filter are
shown in Figure 54 to Figure 64. Figure 57 shows a
detailed view of the filter frequency response from
48Hz to 62Hz for a 20SPS data rate. All filter plots
are generated with 4.096MHz external clock.
Figure 53. Simplified Diagram of the PGA
Table 9. Digital Filter Specifications
(1)
ATTENUATION
NOMINAL ACTUAL –3dB
DATA RATE DATA RATE BANDWIDTH f
IN
= 50Hz ±0.3Hz f
IN
= 60Hz ±0.3Hz f
IN
= 50Hz ±1Hz f
IN
= 60Hz ±1Hz
5SPS 5.018SPS 2.26Hz –106dB –74dB –81dB –69dB
10SPS 10.037SPS 4.76Hz –106dB –74dB –80dB –69dB
20SPS 20.075SPS 14.8Hz –71dB –74dB –66dB –68dB
40SPS 40.15SPS 9.03Hz
80SPS 80.301SPS 19.8Hz
160SPS 160.6SPS 118Hz
320SPS 321.608SPS 154Hz
640SPS 643.21SPS 495Hz
1000SPS 1000SPS 732Hz
2000SPS 2000SPS 1465Hz
(1) Values shown for f
OSC
= 4.096MHz.
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