Datasheet
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SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
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9
To help see the response at lower frequencies, Figure 19
illustrates the response out to 180Hz. Notice that both
50Hz and 60Hz signals are rejected. This feature is very
useful for eliminating power line cycle interference during
measurements. Figure 20 shows the ADS1245 response
around these frequencies.
Frequency (Hz)
Gain (dB)
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
170
180
0
−
20
−
40
−
60
−
80
−
100
−
120
−
140
−
160
−
180
f
CLK
= 2.4576MHz
Figure 19. Frequency Response to 180Hz
Frequency (Hz)
Gain (dB)
50 55 60 6545
−
40
−
50
−
60
−
70
−
80
−
90
−
100
−
110
−
120
f
CLK
= 2.4576MHz
Figure 20. Frequency Response Near
50Hz and 60Hz
The ADS1245 data rate and frequency response scale
directly with CLK frequency. For example, if fCLK
increases from 2.4576MHz to 4.9152MHz, the data rate
increases from 15sps to 30sps while the notches in the
response at 50Hz and 60Hz move out to 100Hz and
120Hz.
SETTLING TIME
The ADS1245 has single-cycle settling. That is, the output
data is fully settled after a single conversion—there is no
need to wait for additional conversions before retrieving
the data when there is a change on the analog inputs.
In order to realize single-cycle settling, synchronize
changes on the analog inputs to the conversion beginning,
which is indicated by the falling edge of DRDY
/DOUT. For
example, when using a multiplexer in front of the
ADS1245, change the multiplexer inputs when
DRDY
/DOUT goes low. Increasing the time between the
conversion beginning and the change on the analog inputs
(t
DELAY
) results in a settling error in the conversion data, as
shown in Figure 21. The settling error versus delay time is
shown in Figure 22. If the input change is delayed to the
point where the settling error is too high, simply ignore the
first data result and wait for the second conversion, which
will be fully settled.
Delay Time, t
DELAY
(ms)
Settling Error (%)
2 4 6 8 101214160
10.000000
1.000000
0.100000
0.010000
0.001000
0.000100
0.000010
0.000001
f
CLK
= 2.4576MHz
Figure 21. Settling Error vs Delay Time