Datasheet

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SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
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13
SLEEP MODE
Sleep mode dramatically reduces power consumption
(typically < 1µW with CLK stopped) by shutting down all of
the active circuitry. To enter Sleep mode, simply hold
SCLK high after DRDY
/DOUT goes low, as shown in
Figure 27. Sleep Mode can be initiated at any time during
read-back; it is not necessary to retrieve all 24 bits of data
beforehand. Once t
11 has passed with SCLK held high,
Sleep mode will activate. DRDY
/DOUT stays high once
Sleep mode begins. SCLK must remain high to stay in
Sleep mode. To exit Sleep mode (wakeup), set SCLK low.
The first data after exiting Sleep Mode is valid. It is not
necessary to stop CLK during Sleep mode, but doing so
will further reduce the digital supply current.
Sleep Mode with Self-Calibration
Self-calibration can be set to run immediately after exiting
Sleep mode. This is useful when the ADS1245 is put in
Sleep mode for long periods of time and self-calibration is
desired afterwards to compensate for temperature or
supply voltage changes.
To force a self-calibration with Sleep mode, shift 25 bits out
before taking SCLK high to enter Sleep mode.
Self-calibration begins after wakeup. Figure 28 shows the
appropriate timing. Note the extra time needed after
wakeup for calibration before data is ready. The first data
after Sleep mode with self-calibration is fully settled and
can be used.
DRDY/DOUT 23 22 21
124
023
SCLK
Sleep Mode
Wakeup
Data ready after wakeup
t
10
t
11
t
12
SYMBOL DESCRIPTION MIN MAX UNITS
NOTES: (1) Values given for f
CLK
= 2.4576MHz. For different CLK frequencies, scale proportional to
CLK period.
t
10
(1)
t
11
(1)
t
12
(1)
SCLK HIGH after DRDY/DOUT goes low to activate Sleep
Mode.
0
66.5
71
66.5
72
ms
ms
ms
Sleep Mode activation time.
Data ready after wakeup.
63.7
Figure 27. Sleep-Mode Timing; Can Be Used for SIngle Conversions
Sleep Mode
Wakeup and begin cal.
Data ready after wakeup and calibration
t
11
t
13
DRDY/DOUT 23
12425
22 21 0 23
SCLK
SYMBOL DESCRIPTION MIN MAX UNITS
t
13
(1)
Data ready after wakeup and calibration.
210 211
ms
NOTE: (1) Values given for f
CLK
= 2.4576MHz. For different CLK frequencies, scale
proportional to CLK period.
Figure 28. Sleep-Mode with Self-Calibration on Wakeup Timing; Can Be Used for SIngle Conversions