Datasheet

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SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
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12
23
12425
22 21 0
Data
25th SCLK to force DRDY/DOUT
Data is ready. New data is ready.
DRDY/DOUT
SCLK
high
Figure 25. Data Retrieval with DRDY/DOUT Forced High Afterwards
SELF-CALIBRATION
The user can initiate self-calibration at any time, though in
many applications the ADS1245 drift performance is good
enough that the self-calibration performing automatically
at power-up is all that is needed. To initiate a
self-calibration, apply at least two additional SCLKs after
retrieving 24 bits of data. Figure 26 shows the timing
pattern. The 25th SCLK will send DRDY
/DOUT high. The
falling edge of the 26th SCLK will begin the calibration
cycle. Additional SCLK pulses may be sent after the 26th
SCLK, but minimizing activity on SCLK during calibration
provides best results.
When the calibration is complete, DRDY
/DOUT will go
low, indicating that new data is ready. There is no need to
alter the analog input signal applied to the ADS1245 during
calibration; the inputs pins are disconnected within the
ADC and the appropriate signals are automatically applied
internally. The first conversion after a calibration is fully
settled and valid for use. The time required for a calibration
depends on two independent signals: the falling edge of
SCLK and an internal clock derived from CLK. Variations
in the internal calibration values will change the time
required for calibration (t
9
) within the range given by the
MIN/MAX specs. t
12
and t
13
described in the next section
are likewise affected.
23DRDY/DOUT
SCLK
124
t
9
25 26
2322 21 0
Data ready after calibration
Cal begins
SYMBOL DESCRIPTION MIN MAX UNITS
t
9
(1)
First data ready after calibration.
209 210
ms
NOTE: (1) Values given for f
CLK
= 2.4576MHz. For different CLK frequencies,
scale proportional to CLK period.
Figure 26. Self-Calibration Timing