Datasheet

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SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003
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10
Begin New Conversion,
Complete Previous Conversion
New Conversion Complete
t
DELAY
DRDY/DOUT
V
IN
Previous Conversion Data
Figure 22. Analog Input Change Timing
POWER−UP
Self-calibration is performed at power-up to minimize offset
and gain errors. In order for the self-calibration at power-up to
work properly, make sure that both AVDD and DVDD increase
monotonically and are settled by t
1
, as shown in Figure 23.
SCLK must be held low during this time. Once calibration
is complete, DRDY
/DOUT goes low, indicating data is
ready for retrieval. The time required before the first data
is ready (t
6
) depends on how fast AVDD and DVDD ramp
to their final value (t
1
). For most ramp rates, t
1
+ t
2
≈ 350ms
(f
CLK
= 2.4576MHz). If the system environment is not stable
during power-up (the temperature is varying or the supply
voltages are moving around), it is recommended that a
self-calibration be issued after everything is stable.
AVDD and DVDD
DRDY/DOUT
SCLK
t
1
t
2
Data ready after power−up calibration.
SYMBOL DESCRIPTION MIN MAX UNITS
t
1
(1)
t
2
(1)
Wait time for calibration and first data
conversion.
316
100 ms
ms
NOTE: (1) Values given for f
CLK
= 2.4576MHz. For different CLK frequencies,
scale proportional to CLK period.
AVDD and DVDD settling time.
Figure 23. Power-Up Timing