Datasheet

ADS1244
7
SBAS273
www.ti.com
OVERVIEW
The ADS1244 is an A/D converter comprised of a 3rd-order
modulator followed by a digital filter. The modulator measures
the differential input signal V
IN
= (AINP – AINN) against the
differential reference V
REF
= (VREFP – VREFN). Figure 1
shows a conceptual diagram. The differential reference is
scaled internally so that the full-scale input range is
±2V
REF
.
The digital filter receives the modulator’s signal and provides
a low-noise digital output. The filter also sets the frequency
response of the converter and provides 50Hz and 60Hz
rejection while settling in a single conversion cycle. A 2-wire
serial interface indicates conversion completion and provides
the user with the output data.
The constant charging of the input capacitors presents a load
on the inputs that can be represented by effective imped-
ances. Figure 4 shows the input circuitry with the capacitors
and switches of Figure 2 replaced by their effective imped-
ances. These impedances scale inversely with f
CLK
fre-
quency. For example, if f
CLK
’s frequency is reduced by a
factor of 2, the impedances will double.
FIGURE 1. Conceptual Diagram of the ADS1244.
Modulator
Digital
Filter and
Serial
Interface
Σ
2
VREFP VREFN
V
REF
Σ
AINN
AINP
DRDY/DOUT
SCLK
CLK
V
IN
2V
REF
ANALOG INPUTS (AINP, AINN)
The input signal to be measured is applied to the input pins
AINP and AINN. The ADS1244 accepts differential input
signals, but can also measure unipolar signals. When mea-
suring unipolar (or “single-ended” signals) with respect to
ground, connect the negative input (AINN) to ground and
connect the input signal to the positive input (AINP). Note
that when the ADS1244 is used this way, only half of the
converter’s full-scale range is used since only positive digital
output codes will be produced.
The ADS1244 measures the input signal using internal
capacitors that are continuously charged and discharged.
Figure 2 shows a simplified schematic of the ADS1244’s
input circuitry with Figure 3 showing the ON/OFF timings of
the switches. S
1
switches close during the input sampling
phase. With S
1
closed, C
A1
charges to AINP, C
A2
charges to
AINN, and C
B
charges to (AINP – AINN). For the discharge
phase, S
1
opens first and then S
2
closes. C
A1
and C
A2
discharge to approximately AVDD/2 and C
B
discharges to
0V. This 2-phase sample/discharge cycle repeats with a
frequency of f
CLK
/128 (19.2kHz for f
CLK
= 2.4576MHz).
FIGURE 2. Simplified Input Structure.
S
1
AVDD
ESD Protection
AINP
AVDD/2
C
A1
= 4pF
C
B
= 8pF
C
A2
= 4pF
S
2
S
1
AVDD
AINN
AVDD/2
S
2
FIGURE 3. S
1
and S
2
Switch Timing for Figure 1.
ON
OFF
ON
S
1
S
2
OFF
t
SAMPLE
= 128/f
CLK
FIGURE 4. Effective Analog Input Impedances.
Zeff
A
= t
SAMPLE
/C
A1
= 13MΩ
(1)
Zeff
B
= t
SAMPLE
/C
B
= 6.5MΩ
(1)
Zeff
A
= t
SAMPLE
/C
A2
= 13MΩ
(1)
NOTE: (1) f
CLK
= 2.4576MHz.
AINP
AINN
AVDD/2
AVDD/2
ESD diodes protect the inputs. To keep these diodes from turning
on, make sure the voltages on the input pins do not go below
GND by more than 100mV, and likewise do not exceed AVDD by
100mV: GND – 100mV < (AINP, AINN) < AVDD + 100mV.