Datasheet

ADS1244
11
SBAS273
www.ti.com
DATA RETRIEVAL
The ADS1244 continuously converts the analog input signal.
To retrieve data, wait until DRDY/DOUT
goes LOW, as
shown in Figure 12. After this occurs, begin shifting out the
data by applying SCLKs. Data is shifted out Most Significant
Bit (MSB) first. It is not required to shift out all the 24 bits of
data, but the data must be retrieved before the new data is
updated (see t
3
) or else it will be overwritten. Avoid data
retrieval during the update period. DRDY/DOUT
will remain
at the state of the last bit shifted out until it is taken HIGH (see
t
7
), indicating that new data is being updated.
To avoid having DRDY/DOUT
remain in the state of the last
bit, shift a 25th SCLK to force DRDY/DOUT
HIGH, see
Figure 13. This technique is useful when a host controlling
the ADS1244 is polling DRDY/DOUT
to determine when
data is ready.
FIGURE 12. Data Retrieval Timing.
DRDY/DOUT 23 22 21
124
0
LSBMSB
Data
Data is ready.
SCLK
t
3
t
8
t
4
t
4
t
7
New data is ready.
t
5
t
6
FIGURE 13. Data Retrieval with DRDY/DOUT Forced HIGH Afterwards.
23
12425
22 21 0
Data
25th SCLK to force DRDY/DOUT HIGH.
Data is ready.
New data is ready.
DRDY/DOUT
SCLK
SYMBOL DESCRIPTION MIN MAX UNITS
t
3
DRDY/DOUT
LOW to first SCLK rising edge. 0 ns
t
4
SCLK positive or negative pulse width. 100 ns
t
5
(1)
SCLK rising edge to new data bit valid: 50 ns
propagation delay.
t
6
SCLK rising edge to old data bit valid: hold time. 0 ns
t
7
(2)
Data updating, no read back allowed. 152 152 µs
t
8
(2)
Conversion time (1/data rate). 66.667 66.667 ms
NOTES: (1) Load on
DRDY/DOUT
= 20pF || 100kΩ. (2) Values given for f
CLK
= 2.4576MHz. For different
CLK frequencies, scale proportional to CLK period. For example, for f
CLK
= 4.9152MHz, t
8
→ 33.333ms.