Datasheet
ADS1242, 1243
14
SBAS235H
www.ti.com
FIGURE 7. Analog/Data Interface Pin.
IOCON
A
IN
x/Dx
To Analog Mux
DIO WRITE
DIR
DIO READ
excess current dissipation. If the pin is configured as an
output in the DIR register, then the corresponding DIO
register bit value determines the state of the output pin
(0 = GND, 1 = V
DD
).
It is still possible to perform A/D conversions on a pin
configured as data I/O. This may be useful as a test mode,
where the data I/O pin is driven and an A/D conversion is
done on the pin.
SERIAL PERIPHERAL INTERFACE
The Serial Peripheral Interface (SPI) allows a controller to
communicate synchronously with the ADS1242 and ADS1243.
The ADS1242 and ADS1243 operate in slave-only mode.
The serial interface is a standard four-wire SPI (
CS
, SCLK,
D
IN
and D
OUT
) interface.
Chip Select (
CS
)
The chip select (
CS
) input must be externally asserted
before communicating with the ADS1242 or ADS1243.
CS
must stay LOW for the duration of the communication.
Whenever
CS
goes HIGH, the serial interface is reset.
CS
may be hard-wired LOW.
Serial Clock (SCLK)
The serial clock (SCLK) features a Schmitt-triggered input
and is used to clock D
IN
and D
OUT
data. Make sure to have
a clean SCLK to prevent accidental double-shifting of the
data. If SCLK is not toggled within three
DRDY
pulses, the
serial interface resets on the next SCLK pulse and starts a
new communication cycle. A special pattern on SCLK resets
the entire chip; see the RESET section for additional informa-
tion.
Data Input (D
IN
) and Data Output (D
OUT
)
The data input (D
IN
) and data output (D
OUT
) receive and send
data from the ADS1242 and ADS1243. D
OUT
is high imped-
ance when not in use to allow D
IN
and D
OUT
to be connected
together and driven by a bidirectional bus. Note: the Read
Data Continuous Mode (RDATAC) command should not be
issued when D
IN
and D
OUT
are connected. While in RDATAC
mode, D
IN
looks for the STOPC or RESET command. If
either of these 8-bit bytes appear on D
OUT
(which is con-
nected to D
IN
), the RDATAC mode ends.
DATA READY (
DRDY
) PIN
The
DRDY
line is used as a status signal to indicate when
data is ready to be read from the internal data register.
DRDY
goes LOW when a new data word is available in the
DOR register. It is reset HIGH when a read operation from
the data register is complete. It also goes HIGH prior to the
updating of the output register to indicate when not to read
from the device to ensure that a data read is not attempted
while the register is being updated.
The status of
DRDY
can also be obtained by interrogating bit
7 of the ACR register (address 2
H
). The serial interface can
operate in 3-wire mode by tying the
CS
input LOW. In this
case, the SCLK, D
IN
, and D
OUT
lines are used to communi-
cate with the ADS1242 and ADS1243. This scheme is
suitable for interfacing to microcontrollers. If
CS
is required
as a decoding signal, it can be generated from a port bit of
the microcontroller.
DSYNC OPERATION
Synchronization can be achieved through the DSYNC
command. When the DSYNC command is sent, the digital
filter is reset on the edge of the last SCLK of the DSYNC
command. The modulator is held in RESET until the next
edge of SCLK is detected. Synchronization occurs on the
next rising edge of the system clock after the first SCLK
following the DSYNC command.
POWER-UP—SUPPLY VOLTAGE RAMP RATE
The power-on reset circuitry was designed to accommodate
digital supply ramp rates as slow as 1V/10ms. To ensure
proper operation, the power supply should ramp monotoni-
cally.