Datasheet

www.ti.com
POWER-UP SEQUENCE
AVDD
DVDD
PDWN
³ m10 s
POWER-DOWN MODE
DVDD
(1)
Connectto
ADS1232/34
pin
PDWN
1kW
2.2nF
NOTE:(1)AVDDmustbepoweredupatleast
10 sbefore goeshigh.m
PDWN
DataReady
Start
Conversion
DRDY/DOUT
SCLK
CLKSoure
WakeupPower-DownMode
PDWN
t
13
t
11
t
14
ADS1232
ADS1234
SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008
When powering up the ADS1232/34, AVDD and
DVDD must be powered up before the PDWN pin
goes high, as shown in Figure 39 . If PDWN is not
controlled by a microprocessor, a simple RC delay
circuit must be implemented, as shown in Figure 40 .
Figure 39. Power-Up Timing Sequence
Power-Down mode shuts down the entire ADC
circuitry and reduces the total power consumption
close to zero. To enter Power-Down mode, simply
hold the PDWN pin low. Power-Down mode also
resets the entire circuitry to free the ADC circuitry
from locking up to an unknown state. Power-Down
mode can be initiated at any time during readback; it
is not necessary to retrieve all 24 bits of data
beforehand. Figure 41 shows the wake-up timing
from Power-Down mode.
Figure 40. RC Delay Circuit
Figure 41. Wake-Up Timing from Power-Down Mode
SYMBOL DESCRIPTION TYP UNITS
Internal clock 7.95 µ s
t
13
Wake-up time after Power-Down mode External clock 0.16 µ s
Crystal oscillator
(1)
5.6 ms
t
14
(2)
PDWN pulse width 26 (min) µ s
(1) No capacitors on CLKIN/XTAL1 or XTAL2 outputs.
(2) Value given for f
CLK
= 4.9152MHz. For different f
CLK
frequencies, the scale is proportional to the CLK period except for a ± 3% variation
when an internal oscillator is used.
Copyright © 2005 – 2008, Texas Instruments Incorporated 23
Product Folder Link(s): ADS1232 ADS1234