Datasheet

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STANDBY MODE
DRDY/DOUT 23 22 21
1 24
0 23
SCLK
Standby Mode
Start Conversion
Data Ready
t
9
t
10
t
11
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SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008
When t
10
has passed with SCLK held high, Standby
mode will activate. DRDY/DOUT stays high when
Standby mode dramatically reduces power
Standby mode begins. SCLK must remain high to
consumption by shutting down most of the circuitry. In
stay in Standby mode. To exit Standby mode
Standby mode, the entire analog circuitry is powered
(wakeup), set SCLK low. The first data after exiting
down and only the clock source circuitry is awake to
Standby mode is valid.
reduce the wake-up time from the Standby mode. To
enter Standby mode, simply hold SCLK high after
DRDY/DOUT goes low; see Figure 37 . Standby mode
can be initiated at any time during readback; it is not
necessary to retrieve all 24 bits of data beforehand.
Figure 37. Standby Mode Timing (can be used for single conversions)
SYMBOL DESCRIPTION MIN MAX UNITS
SPEED = 1 0 12.44 ms
SCLK high after DRDY/DOUT goes low
t
9
(1)
to activate Standby mode
SPEED = 0 0 99.94 ms
SPEED = 1 12.46 ms
t
10
(1)
Standby mode activation time
SPEED = 0 99.96 ms
SPEED = 1 52.51 52.51 ms
t
11
(1)
Data ready after exiting Standby mode
SPEED = 0 401.8 401.8 ms
(1) Values given for f
CLK
= 4.9152MHz. For different f
CLK
frequencies, scale proportional to CLK period. Expect a ± 3% variation when an
internal oscillator is used.
Copyright © 2005 – 2008, Texas Instruments Incorporated 21
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