Datasheet

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OFFSET CALIBRATION

23DRDY/DOUT

SCLK

1 24

25 26

2322 21 0

Data Ready After Calibration

Calibration Begins

ADS1232

ADS1234

SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008

When the calibration is completed, DRDY/DOUT

goes low, indicating that new data are ready. The

Offset calibration can be initiated at any time to

analog input pins are disconnected within the ADC

remove the ADS1232/4 inherited offset error. To

and the appropriate signal is applied internally to

initiate offset calibration, apply at least two additional

perform the calibration. The first conversion after a

SCLKs after retrieving 24 bits of data. Figure 36

calibration is fully settled and valid for use. The offset

shows the timing pattern. The 25th SCLK will send

calibration takes exactly the same time as specified in

DRDY/DOUT high. The falling edge of the 26th SCLK

) right after the falling edge of the 26th SCLK.

will begin the calibration cycle. Additional SCLK

pulses may be sent after the 26th SCLK; however,

activity on SCLK should be minimized during offset

calibration for best results.

Figure 36. Offset-Calibration Timing

SYMBOL DESCRIPTION MIN MAX UNITS

SPEED = 1 101.28 101.29 ms

(1)

First data ready after calibration

SPEED = 0 801.02 801.03 ms

(1) Values given for f

CLK

= 4.9152MHz. For different f

CLK

frequencies, scale proportional to CLK period. Expect a ± 3% variation when an

internal oscillator is used.

Product Folder Link(s): ADS1232 ADS1234