Datasheet

www.ti.com
DATA RETRIEVAL
DRDY/DOUT 23 22 21
1 24
0
LSBMSB
Data
Data Ready
SCLK
t
2
t
7
t
3
t
3
t
6
New Data Ready
t
4
t
5
23
1 24 25
22 21 0
Data
25th SCLK to Force DRDY/DOUT High
Data Ready New Data Ready
DRDY/DOUT
SCLK
ADS1232
ADS1234
SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008
indicating that new data are being updated. To avoid
having DRDY/DOUT remain in the state of the last
The ADS1232/4 continuously convert the analog
bit, the user can shift SCLK to force DRDY/DOUT
input signal. To retrieve data, wait until DRDY/DOUT
high, as shown in Figure 35 . This technique is useful
goes low, as shown in Figure 34 . After this occurs,
when a host controlling the device is polling
begin shifting out the data by applying SCLKs. Data
DRDY/DOUT to determine when data are ready.
are shifted out MSB first. It is not required to shift out
all 24 bits of data, but the data must be retrieved
before new data are updated (within t
7
) or else it will
be overwritten. Avoid data retrieval during the update
period (t
6
). DRDY/DOUT remains at the state of the
last bit shifted out until it is taken high (see t
6
),
Figure 34. Data Retrieval Timing
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
2
DRDY/DOUT low to first SCLK rising edge 0 ns
t
3
SCLK positive or negative pulse width 100 ns
SCLK rising edge to new data bit valid: propagation
t
4
50 ns
delay
t
5
SCLK rising edge to old data bit valid: hold time 0 ns
t
6
(1)
Data updating: no readback allowed 39 µ s
SPEED = 1 12.5 ms
t
7
(1)
Conversion time (1/data rate)
SPEED = 0 100 ms
(1) Values given for f
CLK
= 4.9152MHz. For different f
CLK
frequencies, scale proportional to CLK period.
Figure 35. Data Retrieval with DRDY/DOUT Forced High Afterwards
Copyright © 2005 – 2008, Texas Instruments Incorporated 19
Product Folder Link(s): ADS1232 ADS1234