Datasheet

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DATA RATE DATA READY/DATA OUTPUT ( DRDY/DOUT)
SERIAL CLOCK INPUT (SCLK)
DATA FORMAT
ADS1232
ADS1234
SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008
The ADS1232/4 data rate is set by the SPEED pin, This digital output pin serves two purposes. First, it
as shown in Table 7 . When SPEED is low, the data indicates when new data are ready by going low.
rate is nominally 10SPS. This data rate provides the Afterwards, on the first rising edge of SCLK, the
lowest noise, and also has excellent rejection of both DRDY/DOUT pin changes function and begins
50Hz and 60Hz line-cycle interference. For outputting the conversion data, most significant bit
applications requiring fast data rates, setting SPEED (MSB) first. Data are shifted out on each subsequent
high selects a data rate of nominally 80SPS. SCLK rising edge. After all 24 bits have been
retrieved, the pin can be forced high with an
Table 7. Data Rate Settings additional SCLK. It will then stay high until new data
are ready. This configuration is useful when polling
DATA RATE
on the status of DRDY/DOUT to determine when to
SPEED Internal Oscillator External
begin data retrieval.
PIN or 4.9152MHz Crystal Oscillator
0 10SPS f
CLKIN
/ 491,520
1 80SPS f
CLKIN
/ 61,440
This digital input shifts serial data out with each rising
edge. This input has built-in hysteresis, but care
should still be taken to ensure a clean signal. Glitches
or slow-rising signals can cause unwanted additional
The ADS1232/4 output 24 bits of data in binary two ’ s
shifting. For this reason, it is best to make sure the
complement format. The least significant bit (LSB)
rise-and-fall times of SCLK are less than 50ns.
has a weight of 0.5V
REF
/(2
23
– 1). The positive
full-scale input produces an output code of 7FFFFFh
and the negative full-scale input produces an output
code of 800000h. The output clips at these codes for
signals exceeding full-scale. Table 8 summarizes the
ideal output codes for different input signals.
Table 8. Ideal Output Code vs Input Signal
(1)
INPUT SIGNAL V
IN
(AINP – AINN) IDEAL OUTPUT CODE
≥ +0.5V
REF
/Gain 7FFFFFh
(+0.5V
REF
/Gain)/(2
23
– 1) 000001h
0 000000h
( – 0.5V
REF
/Gain)/(2
23
– 1) FFFFFFh
≤ – 0.5V
REF
/Gain 800000h
(1) Excludes effects of noise, INL, offset, and gain errors.
18 Copyright © 2005 – 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS1232 ADS1234