Datasheet

www.ti.com
SETTLING TIME
A1orA0
t
1
DRDY/DOUT
t
S
ToggledTEMPPinor AbruptChangeinExternalV
IN
V
IN
DRDY/DOUT
Startof
conversion.
1stconversion;
includes
unsettledV .
IN
2ndconversion;
V settled,but
IN
digitalfilter
unsettled.
3rdconversion;
V settled,but
IN
digitalfilter
unsettled.
4thconversion;
V settled,but
IN
digitalfilter
unsettled.
5thconversion;
V anddigital
IN
filterboth
settled.
Conversion
Time
ADS1232
ADS1234
SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008
switching input channels. Another example would be
toggling the TEMP pin, which switches the internal
After changing the input multiplexer, the first data are
AINP, AINN signals to connect to either the external
fully settled. In both the ADS1232/4, the digital filter is
AINPx, AINNx pins or to the TEMP diode (see
allowed to settle after toggling either the A1 or A0 pin.
Figure 26 ).
Toggling any of these digital pins will hold the
DRDY/DOUT line high until the digital filter is fully Note that when settling data, five readings may be
settled. For example, if A0 changes from low to high, required. If the change in input occurs in the middle
selecting a different input channel, DRDY/DOUT of the first conversion, four more full conversions of
immediately goes high, and DRDY/DOUT goes low the fully-settled input are required to get fully-settled
when fully-settled data are ready for retrieval. There data. Discard the first four readings because they
is no need to discard any data. Figure 32 shows the contain only partially-settled data.Figure 33 illustrates
timing of the DRDY/DOUT line as the input the settling time for the ADS1232/4 in Continuous
multiplexer changes. Conversion mode.
In certain instances, large and/or abrupt changes in
input will require four data cycles to settle. One
example of such a change would be an external
multiplexer in front of the ADS1232/4, which can
cause large changes in input voltage simply by
Figure 32. Example of Settling Time After Changing the Input Multiplexer
SYMBOL DESCRIPTION
(1)
MIN MAX UNITS
t
S
Setup time for changing the A1 or A0 pins 40 50 µ s
SPEED = 1 51 51 ms
Settling time ( DRDY/DOUT
t
1
held high)
SPEED = 0 401 401 ms
(1) Values given for f
CLK
= 4.9152MHz. For different f
CLK
frequencies, scale proportional to CLK period. Expect a ± 3% variation when an
internal oscillator is used.
Figure 33. Settling Time in Continuous Conversion Mode
Copyright © 2005 – 2008, Texas Instruments Incorporated 17
Product Folder Link(s): ADS1232 ADS1234