Datasheet

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Bypass Capacitor
LOW-NOISE PGA
VOLTAGE REFERENCE INPUTS
Z
EFF
+
1
2f
MOD
C
BUF
R
INT
R
INT
R
F1
R
1
R
F2
ADC
A3
Gainof1or2
CAP
AINP
AINN
CAP
A2
A1
450W
18pF
450W
18pF
ADS1232
ADS1234
SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008
By applying a 0.1µF external capacitor (C
EXT
) across
The ADS1232/4 features a low-drift, low-noise PGA
two capacitor pins and the combination of the internal
that provides a complete front-end solution for bridge
2k Ω resistor R
INT
on-chip, a low-pass filter (with a
sensors. A simplified diagram of the PGA is shown in
corner frequency of 720Hz) is created to bandlimit the
Figure 27 . It consists of two chopper-stabilized
signal path prior to the modulator input. This low-pass
amplifiers (A1 and A2) and three accurately-matched
filter serves two purposes. First, the input signal is
resistors (R
1
, R
F1
, and R
F2
), which construct a
bandlimited to prevent aliasing as well as to filter out
differential front-end stage with a gain of 64, followed
the high-frequency noise. Second, it attenuates the
by gain stage A3. The PGA inputs are equipped with
chopping residue from the PGA (for gains of 64 and
an EMI filter, as shown in Figure 27 . The cut-off
128 only) to improve temperature drift performance. It
frequency of the EMI filter is 19.6MHz. If the PGA is
is not required to use high quality capacitors (such as
set to 1 or 2, the gain-of-64 stage is bypassed and
ceramic or tantalum capacitors) for a general
shut down to save power. With the combination of
application. However, high quality capacitors such as
both gain stages, the PGA can be set to 64 or 128.
poly are recommended for high linearity applications.
The PGA of the ADS1232/4 can be set to 1, 2, 64, or
128 with pins GAIN1 (MSB) and GAIN0 (LSB). By
using AVDD as the reference input, the bipolar input
ranges from ± 2.5V to ± 19.5mV, while the unipolar (REFP, REFN)
ranges from 2.5V to 19.5mV. When the PGA is set to
The voltage reference used by the modulator is
1 or 2, the absolute inputs can go rail-to-rail without
generated from the voltage difference between REFP
significant performance degradation. However, the
and REFN: V
REF
= REFP – REFN. The reference
inputs of the ADS1232/4 are protected with internal
inputs use a structure similar to that of the analog
diodes connected to the power-supply rails. These
inputs. In order to increase the reference input
diodes will clamp the applied signal to prevent it from
impedance, a switching buffer circuitry is used to
damaging the input circuitry. On the other hand, when
reduce the input equivalent capacitance. The
the PGA is set to 64 or 128, the operating input range
reference drift and noise impact ADC performance. In
is limited to (AGND + 1.5V) to (AVDD – 1.5V), in
order to achieve best results, pay close attention to
order to prevent saturating the differential front-end
the reference noise and drift specifications. A
circuitry and degrading performance.
simplified diagram of the circuitry on the reference
inputs is shown in Figure 28 . The switches and
capacitors can be modeled with an effective
impedance of:
Where:
f
MOD
= modulator sampling frequency (76.8kHz)
C
BUF
= input capacitance of the buffer
For the ADS1232/4:
Figure 27. Simplified Diagram of the PGA
14 Copyright © 2005 – 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS1232 ADS1234