Datasheet

DRDY/DOUT
23
22 21
1 24
0 23
SCLK
StandbyMode
DataReady
t
DSS
t
STANDBY
t
S_RDY
StartConversion
23
1 24 25
22 21 0
Data
25thSCLKtoForce /DOUTHighDRDY
DataReady NewDataReady
DRDY/DOUT
SCLK
ADS1231
SBAS414D –JULY 2009–REVISED OCTOBER 2013 www.ti.com
STANDBY MODE
When t
STANDBY
has passed with SCLK held high,
Standby mode dramatically reduces power Standby mode activates. DRDY/DOUT stays high
consumption by shutting down most of the circuitry. when Standby mode begins. SCLK must remain high
To enter Standby mode, simply hold SCLK high after to stay in Standby mode. To exit Standby mode
DRDY/DOUT goes low; see Figure 21. Standby mode (wake up), set SCLK low. The first data after exiting
can be initiated at any time during readback; it is not Standby mode are valid.
necessary to retrieve all 24 bits of data beforehand.
Figure 20. Data Retrieval with DRDY/DOUT Forced High Afterwards
Figure 21. Standby Mode Timing (Can be used for single conversions)
SYMBOL DESCRIPTION MIN TYP MAX UNITS
SCLK high after DRDY/DOUT SPEED = 1 12.44 ms
t
DSS
(1)
goes low to activate Standby
SPEED = 0 99.94 ms
mode
SPEED = 1 12.5 ms
t
STANDBY
Standby mode activation time
SPEED = 0 100 ms
SPEED = 1 52.6 ms
Data ready after exiting Standby
t
S_RDY
(1)
mode
SPEED = 0 401.8 ms
(1) Based on an ideal internal oscillator.
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