Datasheet

AbruptChangeinExternalV
IN
V
IN
DRDY/DOUT
Startof
Conversion
Conversion
including
unsettledV .
IN
1stConversion;
V settled,but
digitalfilter
unsettled.
IN
2ndConversion;
V settled,but
digitalfilter
unsettled.
IN
3rdConversion;
V settled,but
digitalfilter
unsettled.
IN
4thConversion;
V settled,but
digitalfilter
unsettled.
IN
Conversion
Time
ADS1231
SBAS414D –JULY 2009–REVISED OCTOBER 2013 www.ti.com
Table 2. Data Rate Settings
SETTLING TIME
DATA RATE
Fast changes in the input signal require time to settle.
SPEED PIN Internal Oscillator External Clock
For example, an external multiplexer in front of the
ADS1231 can generate abrupt changes in input
0 10SPS f
CLKIN
/ 491,520
voltage by simply switching the multiplexer input
1 80SPS f
CLKIN
/ 61,440
channels. These sorts of changes in the input require
four data conversion cycles to settle. When
DATA FORMAT
continuously converting, five readings may be
necessary in order to settle the data. If the change in
The ADS1231 outputs 24 bits of data in binary twos
input occurs in the middle of the first conversion, four
complement format. The least significant bit (LSB)
more full conversions of the fully-settled input are
has a weight of (0.5V
REF
/128)(2
23
– 1). The positive
required to obtain fully-settled data. Discard the first
full-scale input produces an output code of 7FFFFFh
four readings because they contain only partially-
and the negative full-scale input produces an output
settled data. Figure 18 illustrates the settling time for
code of 800000h. The output clips at these codes for
the ADS1231.
signals exceeding full-scale. Table 3 summarizes the
ideal output codes for different input signals.
DATA RATE
Table 3. Ideal Output Code vs Input Signal
The ADS1231 data rate is set by the SPEED pin, as
INPUT SIGNAL V
IN
shown in Table 2. When SPEED is low, the data rate
(AINP – AINN) IDEAL OUTPUT
is nominally 10SPS. This data rate provides the
≥ +0.5V
REF
/128 7FFFFFh
lowest noise, and also has excellent rejection of both
000001h
(+0.5V
REF
/128)/(2
23
– 1)
50Hz and 60Hz line-cycle interference. For
applications requiring fast data rates, setting SPEED
0 000000h
high selects a data rate of nominally 80SPS.
FFFFFFh
(–0.5V
REF
/128)/(2
23
– 1)
≤ –0.5V
REF
/128 800000h
1. Excludes effects of noise, INL, offset, and gain
errors.
Figure 18. Settling Time in Continuous Conversion Mode
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