Datasheet

DataReady
Start
Conversion
DRDY/DOUT
SCLK
CLKSource
Wakeup
Power-DownMode
PDWN
t
WAKEUP
t
TS_RDY
t
PDWN
DVDD
(1)
Connectto
ADS1230
pin
PDWN
1.2kW
2.2nF
NOTE:(1)AVDDmustbepoweredupatleast10
beforePDWNgoeshigh.
ms
AVDD
DVDD
PDWN
³ m10 s
ADS1230
www.ti.com SBAS366B –OCTOBER 2006–REVISED SEPTEMBER 2012
POWER-UP SEQUENCE blank
When powering up the ADS1230, AVDD and DVDD
must be powered up before the PDWN pin goes high,
as shown in Figure 30. If PDWN is not controlled by a
microprocessor, a simple RC delay circuit must be
implemented, as shown in Figure 31.
POWER-DOWN MODE
Figure 30. Power-Up Timing Sequence
Power-Down mode shuts down the entire ADC
circuitry and reduces the total power consumption
close to zero. To enter Power-Down mode, simply
hold the PDWN pin low. Power-Down mode also
resets the entire circuitry to free the ADC circuitry
from locking up to an unknown state. Power-Down
mode can be initiated at any time during readback; it
is not necessary to retrieve all 20 bits of data
beforehand. Figure 32 shows the wake-up timing
from Power-Down mode.
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Figure 31. RC Delay Circuit
Figure 32. Wake-Up Timing from Power-Down Mode
SYMBOL DESCRIPTION MIN TYP UNITS
Internal clock 7.95 μs
Wake-up time after Power-Down
t
WAKEUP
mode
External clock 0.16 μs
t
PDWN
(1)
PDWN pulse width 26 μs
(1) Value given for f
CLK
= 4.9152MHz. For different f
CLK
frequencies, scale proportional to CLK period. Expect a ±3% variation when an
internal oscillator is used.
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