Datasheet

DRDY/DOUT 19 18 17
1 20
0 19
SCLK
StandbyMode
DataReady
t
DSS
t
STANDBY
t
S_RDY
StartConversion
ADS1230
www.ti.com SBAS366B –OCTOBER 2006–REVISED SEPTEMBER 2012
STANDBY MODE When t
STANDBY
has passed with SCLK held high,
Standby mode activates. DRDY/DOUT stays high
Standby mode dramatically reduces power
when Standby mode begins. SCLK must remain high
consumption by shutting down most of the circuitry. In
to stay in Standby mode. To exit Standby mode
Standby mode, the entire analog circuitry is powered
(wakeup), set SCLK low. The first data after exiting
down and only the clock source circuitry is awake to
Standby mode is valid.
reduce the wake-up time from the Standby mode. To
enter Standby mode, simply hold SCLK high after
DRDY/DOUT goes low; see Figure 28. Standby mode
can be initiated at any time during readback; it is not
necessary to retrieve all 20 bits of data beforehand.
Figure 28. Standby Mode Timing (can be used for single conversions)
SYMBOL DESCRIPTION MIN MAX UNITS
SPEED = 1 0 12.44 ms
SCLK high after DRDY/DOUT goes low
t
DSS
(1)
to activate Standby mode
SPEED = 0 0 99.94 ms
SPEED = 1 20 μs
t
STANDBY
(1)
Standby mode activation time
SPEED = 0 20 μs
SPEED = 1 52.51 52.51 ms
t
S_RDY
(1)
Data ready after exiting Standby mode
SPEED = 0 401.8 401.8 ms
(1) Value given for f
CLK
= 4.9152MHz. For different f
CLK
frequencies, scale proportional to CLK period. Expect a ±3% variation when an
internal oscillator is used.
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