Datasheet

19DRDY/DOUT
SCLK
1
23 24 25 26
20
t
CAL
21 22
3 4
1 2
1918 17 0
DataReadyAfterCalibration
CalibrationBegins
ADS1230
SBAS366B –OCTOBER 2006–REVISED SEPTEMBER 2012 www.ti.com
OFFSET CALIBRATION During this time, the analog input pins are
disconnected within the ADC and the appropriate
Offset calibration can be initiated at any time to
signal is applied internally to perform the calibration.
remove the ADS1230 inherited offset error. To initiate
When the calibration is completed, DRDY/DOUT
offset calibration, apply at least two additional SCLKs
goes low, indicating that new data are ready. The first
after retrieving 20 bits of data plus four bits of '1'.
conversion after a calibration is fully settled and valid
Figure 27 shows the timing pattern. The 25th SCLK
for use. The offset calibration takes exactly the same
keeps DRDY/DOUT high. The falling edge of the 26th
time as specified in (t
CAL
) immediately after the falling
SCLK begins the calibration cycle. Additional SCLK
edge of the 26th SCLK.
pulses may be sent after the 26th SCLK; however,
activity on SCLK should be minimized during offset
calibration for best results.
Figure 27. Offset-Calibration Timing
SYMBOL DESCRIPTION MIN MAX UNITS
SPEED = 1 101.28 101.29 ms
t
CAL
(1)
First data ready after calibration
SPEED = 0 801.02 801.03 ms
(1) Value given for f
CLK
= 4.9152MHz. For different f
CLK
frequencies, scale proportional to CLK period. Expect a ±3% variation when an
internal oscillator is used.
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