Datasheet

ADS1230
SBAS366B OCTOBER 2006REVISED SEPTEMBER 2012
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DATA READY/DATA OUTPUT (DRDY/DOUT) DATA RETRIEVAL
This digital output pin serves two purposes. First, it The ADS1230 continuously converts the analog input
indicates when new data are ready by going low. signal. To retrieve data, wait until DRDY/DOUT goes
Afterwards, on the first rising edge of SCLK, the low, as shown in Figure 25. After DRDY/DOUT goes
DRDY/DOUT pin changes function and begins low, begin shifting out the data by applying SCLKs.
outputting the conversion data, most significant bit Data are shifted out MSB first. It is not required to
(MSB) first. Data are shifted out on each subsequent shift out all 20 bits of data, but the data must be
SCLK rising edge. After all 20 bits have been retrieved before new data are updated (within t
CONV
)
retrieved, the pin can be forced high with an or else the data will be overwritten. Avoid data
additional SCLK. It then stays high until new data are retrieval during the update period (t
UPDATE
). If 24
ready. This configuration is useful when polling on the SCLKs have been applied, DRDY/DOUT will be high
status of DRDY/DOUT to determine when to begin since the last four bits have been appended by '1'.
data retrieval. However, if only 20 SCLKs have been applied,
DRDY/DOUT remains at the state of the last bit
shifted out until it is taken high (see t
UPDATE
),
SERIAL CLOCK INPUT (SCLK)
indicating that new data are being updated. To avoid
This digital input shifts serial data out with each rising
having DRDY/DOUT remain in the state of the last
edge. This input has built-in hysteresis, but care
bit, the 21st SCLK can be applied to force
should still be taken to ensure a clean signal. Glitches
DRDY/DOUT high, as shown in Figure 26. This
or slow-rising signals can cause unwanted additional
technique is useful when a host controlling the device
shifting. For this reason, it is best to make sure the
is polling DRDY/DOUT to determine when data are
rise and fall times of SCLK are both less than 50ns.
ready.
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