Datasheet

DRDY/DOUT 19 18 17
1 2 3 20 21 22 23 24
0
LSBMSB
DataReady
SCLK
NewDataReady
1 2
3
4
Data
AbruptChangeinExternalV
IN
V
IN
DRDY/DOUT
Startof
Conversion
1stConversion;
includes
unsettledV .
IN
2ndConversion;
V settled,but
IN
digitalfilter
unsettled.
3rdConversion;
V settled,but
IN
digitalfilter
unsettled.
4thConversion;
V settled,but
IN
digitalfilter
unsettled.
5thConversion;
V anddigital
IN
filterboth
settled.
Conversion
Time
ADS1230
www.ti.com SBAS366B –OCTOBER 2006–REVISED SEPTEMBER 2012
SETTLING TIME DATA FORMAT
In certain instances, large changes in input will The ADS1230 outputs 20 bits of data in binary two’s
require settling time. For example, an external complement format. The least significant bit (LSB)
multiplexer in front of the ADS1230 can put large has a weight of 0.5V
REF
/(2
19
– 1). The positive full-
changes in input voltage by simply switching the scale input produces an output code of 7FFFFh and
multiplexer input channels. Abrupt changes in the the negative full-scale input produces an output code
input will require four data conversion cycles to settle. of 800000h. The output clips at these codes for
When continuously converting, five readings may be signals exceeding full-scale. Table 4 summarizes the
necessary in order to settle the data. If the change in ideal output codes for different input signals.
input occurs in the middle of the first conversion, four
The ADS1230 is a 20-bit ADC. After data conversion
more full conversions of the fully-settled input are
is completed, applying 20 SCLKs retrieves 20 bits of
required to get fully-settled data. Discard the first four
data (MSB first). However, if the SCLKs continue to
readings because they contain only partially-settled
be applied after 20 bits of data are retrieved, the
data. Figure 23 illustrates the settling time for the
DOUT pin outputs four 1s for the 21st through the
ADS1230 in Continuous Conversion mode.
24th SCLK, as shown in Figure 24.
DATA RATE
Table 4. Ideal Output Code vs Input Signal
The ADS1230 data rate is set by the SPEED pin, as
INPUT SIGNAL V
IN
shown in Table 3. When SPEED is low, the data rate
(AINP – AINN) IDEAL OUTPUT
is nominally 10SPS. This data rate provides the
≥ +0.5V
REF
/Gain 7FFFFh
lowest noise, and also has excellent rejection of both
00001h
(+0.5V
REF
/Gain)/(2
19
– 1)
50Hz and 60Hz line-cycle interference. For
0 00000h
applications requiring fast data rates, setting SPEED
FFFFFh
(–0.5V
REF
/Gain)/(2
19
– 1)
high selects a data rate of nominally 80SPS.
≤ –0.5V
REF
/Gain 80000h
Table 3. Data Rate Settings
(1) Excludes effects of noise, INL, offset, and
gain errors.
DATA RATE
SPEED Internal Oscillator External
PIN or 4.9152MHz Crystal Oscillator
0 10SPS f
CLKIN
/ 491,520
1 80SPS f
CLKIN
/ 61,440
Figure 23. Settling Time in Continuous Conversion Mode
Figure 24. Data Retrieval Format
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