Datasheet

Frequency(Hz)
Gain(dB)
0
-50
-100
-150
0 10 20 30 40 50 60 70 80 90 100
(a)
Frequency(Hz)
(b)
Gain(dB)
-50
-100
-150
494846 47 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
DataRate=10SPS
DataRate=10SPS
Frequency(kHz)
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
-200
38.4 76.8
0
f =4.9152MHz
CLK
Gain(dB)
ADS1230
SBAS366B –OCTOBER 2006–REVISED SEPTEMBER 2012 www.ti.com
FREQUENCY RESPONSE
The ADS1230 uses a sinc
4
digital filter with the
frequency response (f
CLK
= 4.9152MHz) shown in
Figure 21. The frequency response repeats at
multiples of the modulator sampling frequency of
76.8kHz. The overall response is that of a low-pass
filter with a –3dB cutoff frequency of 3.32Hz with the
SPEED pin tied low (10SPS data rate) and 11.64Hz
with the SPEED pin tied high (80SPS data rate).
Figure 21. Frequency Response
To help see the response at lower frequencies,
Figure 22(a) illustrates the response out to 100Hz,
when the data rate = 10SPS. Notice that signals at
multiples of 10Hz are rejected, and therefore
simultaneous rejection of 50Hz and 60Hz is achieved.
Figure 22. Frequency Response Out To 100Hz
The benefit of using a sinc
4
filter is that every
frequency notch has four zeros on the same location.
The ADS1230 data rate and frequency response
This response, combined with the low drift internal
scale directly with clock frequency. For example, if
oscillator, provides an excellent normal-mode
f
CLK
increases from 4.9152MHz to 6.144MHz when
rejection of line-cycle interference.
the SPEED pin is tied high, the data rate increases
Figure 22(b) shows the same plot, but zooms in on
from 80SPS to 100SPS, while notches also increase
the 50Hz and 60Hz notches with the SPEED pin tied
from 80Hz to 100Hz. Note that these changes are
low (10SPS data rate). With only a ±3% variation of
only possible when the external clock source is
the internal oscillator, over 100dB of normal-mode
applied.
rejection is achieved.
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