Datasheet

SELF-CALIBRATION
23DRDY/DOUT
SCLK
1 24
t
CAL
25 26
2322 21 0
DataReadyAfterCalibration
CalibrationBegins
START
High
ADS1225
ADS1226
SBAS346C – MAY 2006 – REVISED JANUARY 2009 ....................................................................................................................................................... www.ti.com
When the calibration is complete, DRDY/DOUT goes
low, indicating that new data is ready. There is no
Self-calibration can be initiated at any time by
need to alter the analog input signal applied to the
applying two additional SCLKs after retrieving 24 bits
ADS1225 and ADS1226 during calibration; the input
of data; however, the START pin must be kept high
pins are disconnected within the A/D converter and
prior to data conversion and remain high until the
the appropriate signals are applied internally and
calibration completes. Figure 30 and Table 6 illustrate
automatically. The first conversion after a calibration
the timing pattern. The 25th SCLK will send
is fully settled and valid for use. The time required for
DRDY/DOUT high. The falling edge of the 26th SCLK
a calibration depends on two independent signals:
will begin the calibration cycle. Additional SCLK
the falling edge of SCLK and an internal clock derived
pulses may be sent after the 26th SCLK; however,
from CLK. Variations in the internal calibration values
activity on SCLK should be minimized during
change the time required for calibration (t
CAL
) within
calibration for best results.
the range given by the min/max specs.
Figure 30. Self-Calibration Timing
Table 6. Self-Calibration Time for Figure 30
SYMBOL DESCRIPTION MIN MAX UNITS
t
CAL
First data ready after calibration 187 313 ms
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