Datasheet

DATA RETRIEVAL
DRDY/DOUT 23 22 21
1 24
0
LSBMSB
Data
DataReady
SCLK
STARTTiedHigh
t
DS
t
CONV
t
SCLK
t
SCLK
t
UP
NewDataReady
t
PD
t
HD
23
1 24 25
22 21 0
Data
25thSCLKtoForce /DOUTHighDRDY
DataReady NewDataReady
DRDY/DOUT
SCLK
ADS1225
ADS1226
www.ti.com ....................................................................................................................................................... SBAS346C – MAY 2006 – REVISED JANUARY 2009
Avoid data retrieval during the update period.
DRDY/DOUT remain at the state of the last bit shifted
With the START pin high, the ADS1225 and
out until it is taken high (see t
6
), indicating that new
ADS1226 continuously convert the analog input
data is being updated. To avoid having DRDY/DOUT
signal. To retrieve data, wait until DRDY/DOUT goes
remain in the state of the last bit, shift a 25th SCLK to
low, as illustrated in Figure 28 and Table 5 . After this
force DRDY/DOUT high (refer to Figure 29 ). This
occurs, begin shifting out the data by applying
technique is useful when a host controlling the
SCLKs. Data is shifted out MSB first. It is not required
ADS1225 and ADS1226 is polling DRDY/DOUT to
to shift out all 24 bits of data, but the data must be
determine when data is ready.
retrieved before the new data is updated (see t
2
) or
else it will be overwritten.
Figure 28. Data Retrieval Timing
Table 5. Data Retrieval Times for Figure 28
SYMBOL DESCRIPTION MIN MAX UNITS
t
DS
DRDY/DOUT low to first SCLK rising edge 0 ns
t
SCLK
SCLK positive or negative pulse width 100 ns
t
PD
SCLK rising edge to new data bit valid: propagation delay 50 ns
t
HD
SCLK rising edge to old data bit valid: hold time 0 ns
t
UP
Data updating: no readback allowed 29.5 49.2 µ s
t
CONV
Conversion time (1/data rate), High-Speed mode 8.0 13.3 ms
Conversion time (1/data rate), High-Resolution mode 45.5 83.3 ms
Figure 29. Data Retrieval with DRDY/DOUT Forced High Afterwards
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Product Folder Link(s): ADS1225 ADS1226