Datasheet

)V
REF
2
23
* 1
*V
REF
2
23
* 1
DATA FORMAT
v *V
REF
ǒ
2
23
2
23
* 1
Ǔ
DRDY/DOUT
START
ADS1225/6
Status
SCLKheldlowinthisexample.
DataReady DataReady
Converting Converting Converting
Converting
ADS1225
ADS1226
SBAS346C – MAY 2006 – REVISED JANUARY 2009 ....................................................................................................................................................... www.ti.com
Table 4. Ideal Output Code vs Input Signal
The ADS1225 and ADS1226 can be configured to
continuously convert by holding the START pin high
Input Signal V
IN
as shown in Figure 27 . With START held high, a new
(AINP – AINN) IDEAL OUTPUT CODE
(
(1)
)
conversion starts immediately after the previous
≥ +V
REF
7FFFFFh
conversion completes. This configuration continues
until the START pin is taken low. During calibration,
000001h
the START pin must be kept high. Refer to the
Self-Calibration section for details. Note that when
START is low, the buffer must be disabled to prevent
0 000000h
loading of the inputs.
FFFFFFh
The ADS1225 and ADS1226 output 24 bits of data in
binary twos complement format. The least significant
800000h
bit (LSB) has a weight of (V
REF
)/(2
23
– 1). The
positive full-scale input produces an output code of
7FFFFFh and the negative full-scale input produces
an output code of 800000h. The output clips at these
codes for signals exceeding full-scale. Table 4
summarizes the ideal output codes for different input
signals. (1) Excludes effects of noise, INL, offset, and gain errors.
Figure 27. Conversion with the START Pin High
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