Datasheet

INTERNAL OSCILLATOR MODE
DATA READY/DATA OUTPUT ( DRDY/DOUT)
START
SERIAL CLOCK INPUT (SCLK)
DRDY/DOUT
START
SCLK
ADS1225/6
Status
Shutdown
ConversionData
Converting
t
CONV
t
START
ADS1225
ADS1226
www.ti.com ....................................................................................................................................................... SBAS346C – MAY 2006 – REVISED JANUARY 2009
The ADS1225 and ADS1226 have an internal The ADS1225 and ADS1226 have two modes of
oscillator and run without an external crystal or operation, allowing for High-Speed or
oscillator. High-Resolution. By taking the MODE pin high, the
data rate is approximately 100Hz with an rms noise of
15 µ V. When the MODE pin is low, the ADS1225 and
ADS1226 average multiple samples to increase the
This digital output pin serves two purposes. First, it
noise performance to 4 µ V of rms noise with a data
indicates when new data is ready by going LOW.
rate of 16Hz. Table 2 shows the MODE pin operation.
Afterwards, on the first rising edge of SCLK, the
DRDY/DOUT pin changes function and begins to
Table 2. MODE Pin Operation for the ADS1225
output the conversion data, most significant bit (MSB)
and ADS1226
first. Data is shifted out on each subsequent SCLK
MODE PIN MODE DATA RATE NOISE
rising edge. After all 24 bits have been retrieved, the
0 High-Resolution 16SPS 4 µ Vrms
pin can be forced high with an additional SCLK. It
then stays high until new data is ready. This
1 High-Speed 100SPS 15 µ Vrms
configuration is useful when polling on the status of
DRDY/DOUT to determine when to begin data
retrieval.
The START pin provides easy and precise control of
conversions. Pulse the START pin high to begin a
conversion as shown in Figure 26 and Table 3 . The
This digital input shifts serial data out with each rising
completion of the conversion is indicated by the
edge. There is hysteresis built into this input, but care
DRDY/DOUT pin going low. Once the conversion
should still be taken to ensure a clean signal. Glitches
completes, the ADS1225 and ADS1226 automatically
or slow-rising signals can cause unwanted additional
shut down to save power. They stay shut down until
shifting. For this reason, it is best to make sure the
START is once again taken high to begin a new
rise-and-fall times of SCLK are less than 50ns.
conversion.
Figure 26. Controlling Conversion with the START Pin
Table 3. START Pin Conversion Times for Figure 26
SYMBOL DESCRIPTION MIN MAX UNITS
t
START
Minimum START pulse to initiate a conversion 17 µ s
t
CONV
Conversion time High-Speed mode 8.0 13.3 ms
Conversion time High-Resolution mode 45.5 83.3 ms
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Product Folder Link(s): ADS1225 ADS1226