Datasheet

ADS1220EVM Hardware Details

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5.4.2 JTAG Connector, J10

Firmware downloading and debugging is possible through JTAG connector J10. The 14-pin connector of

the MSP-FET430UIF debug interface is reduced to a minimum number of pins to limit connector size and

space available on the EVM. The J10 logic levels are 3.3-V CMOS. A four-wire JTAG interface is

available. Table 9 shows a comparison between the 14-pin debugger connections in relation to J10. The

information can be used to create an adapter between J10 and the 14-pin debugger cable. The J10

footprint is a 2-mm pitch spacing if a socket or header is used.

Table 9. JTAG Interface Connections

Function Debugger Connector Pin Number (J10)

GND Pin 9 8

N/C Pin 6 n/a

N/C Pin 10 n/a

N/C Pin 12 n/a

N/C Pin 13 n/a

N/C Pin 14 n/a

RST Pin 11 7

TCK Pin 7 5

TDI/VPP Pin 3 3

TDO/TDI Pin 1 2

TEST/VPP Pin 8 6

TMS Pin 5 4

VCC debugger Pin 2 1

VCC target Pin 4 n/a

ADS1x20EVM SBAU203–July 2013

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