Datasheet

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TIMING SPECIFICATIONS
t
4
MSB
(Command or Command and Data)
LSB
t
5
t
1
t
3
CS
SCLK
(POL = 0)
D
IN
D
OUT
NOTE: (1) Bit Order = 0.
t
7
MSB
(1)
LSB
(1)
t
8
t
10
t
2
t
2
t
11
t
6
t
9
SCLK
(POL = 1)
TIMING SPECIFICATION TABLE
ADS1218
SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005
SPEC DESCRIPTION MIN MAX UNIT
t
1
SCLK Period 4 t
OSC
Periods
3 DRDY Periods
t
2
SCLK Pulse Width, High and Low 200 ns
t
3
CS Low to first SCLK Edge; Setup Time 0 ns
t
4
D
IN
Valid to SCLK Edge; Setup Time 50 ns
t
5
Valid D
IN
to SCLK Edge; Hold Time 50 ns
t
6
Delay between last SCLK edge for D
IN
and first SCLK edge for D
OUT
:
RDATA, RDATAC, RREG, WREG, RRAM 50 t
OSC
Periods
CSREG, CSRAMX, CSRAM 200 t
OSC
Periods
CSARAM, CSARAMX 1100 t
OSC
Periods
t
7
(1)
SCLK Edge to Valid New D
OUT
50 ns
t
8
(1)
SCLK Edge to D
OUT
, Hold Time 0 ns
t
9
Last SCLK Edge to D
OUT
Tri-State 6 10 t
OSC
Periods
NOTE: D
OUT
goes tri-state immediately when CS goes High.
t
10
CS Low time after final SCLK edge 0 ns
t
11
Final SCLK edge of one op code until first edge SCLK of next command:
RREG, WREG, RRAM, WRAM, CSRAMX, CSARAMX, CSRAM, CSARAM, 4 t
OSC
Periods
CSREG, SLEEP, RDATA, RDATAC, STOPC
DSYNC 16 t
OSC
Periods
CSFL 33,000 t
OSC
Periods
CREG, CRAM 220 t
OSC
Periods
RF2R 1090 t
OSC
Periods
CREGA 1600 t
OSC
Periods
WR2F 76,850 (SPEED = 0) t
OSC
Periods
101,050 (SPEED = 1) 4 t
OSC
Periods
SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL 7 DRDY Periods
SELFCAL 14 DRDY Periods
RESET (Command, SCLK, or Pin) 2640 t
OSC
Periods
(1) Load = 20pF | | 10k Ω to DGND.
9