Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- ELECTRICAL CHARACTERISTICS: AVDD = 5V
- ELECTRICAL CHARACTERISTICS: AVDD = 3V
- DIGITAL CHARACTERISTICS: TMIN to TMAX, DVDD = 2.7V to 5.25V
- FLASH CHARACTERISTICS: TMIN to TMAX, DVDD = 2.7V to 5.25V, unless otherwise specified.
- PIN CONFIGURATION
- TIMING SPECIFICATIONS
- TIMING SPECIFICATION TABLE
- TIMING SPECIFICATION TABLE
- TYPICAL CHARACTERISTICS
- OVERVIEW
- INPUT MULTIPLEXER
- TEMPERATURE SENSOR
- BURNOUT CURRENT SOURCES
- INPUT BUFFER
- IDAC1 AND IDAC2
- PGA
- PGA OFFSET DAC
- MODULATOR
- VOLTAGE REFERENCE INPUT
- ON-CHIP VOLTAGE REFERENCE
- VRCAP PIN
- CLOCK GENERATOR
- CALIBRATION
- DIGITAL FILTER
- DIGITAL I/O INTERFACE
- SERIAL PERIPHERAL INTERFACE
- DATA READY
- DSYNC OPERATION
- MEMORY
- REGISTER BANK
- RAM
- FLASH
- REGISTER MAP
- COMMAND DEFINITIONS

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ELECTRICAL CHARACTERISTICS: AV
DD
= 3V
ADS1218
SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005
All specifications T
MIN
to T
MAX
, AV
DD
= +3V, DV
DD
= +2.7V to 5.25V, f
MOD
= 19.2kHz, f
OSC
= 2.4576MHz, PGA = 1, Buffer On,
R
DAC
= 75k Ω , V
REF
≡ (REF IN+) – (REF IN–) = +1.25V, and f
DATA
= 10Hz, unless otherwise specified.
ADS1218
PARAMETER CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT (A
IN
0 – A
IN
7, A
INCOM
)
Analog Input Range Buffer Off AGND – 0.1 AV
DD
+ 0.1 V
Buffer On AGND + 0.05 AV
DD
– 1.5 V
Full-Scale Input Voltage Range (In+) – (In–), See Block Diagram ±V
REF
/PGA V
Input Impedance Buffer Off 5/PGA M Ω
Input Current Buffer On 0.5 nA
Bandwidth
Fast Settling Filter –3dB 0.469 × f
DATA
Hz
–3dB 0.318 × f
DATA
Hz
Sinc
2
Filter
–3dB 0.262 × f
DATA
Hz
Sinc
3
Filter
Programmable Gain Amplifier User-Selectable Gain Ranges 1 128
Input Capacitance 9 pF
Input Leakage Current Modulator Off, T = +25°C 5 pA
Burnout Current Sources 2 µA
OFFSET DAC
Offset DAC Range ±V
REF
/(2 × PGA) V
Offset DAC Monotonicity 8 Bits
Offset DAC Gain Error ±10 %
Offset DAC Gain Error Drift 2 ppm/°C
SYSTEM PERFORMANCE
Resolution 24 Bits
No Missing Codes 24 Bits
Integral Nonlinearity End Point Fit ±0.0015 % of FS
Offset Error
(1)
Before Calibration 15 ppm of FS
Offset Drift
(1)
0.04 ppm of FS/°C
Gain Error After Calibration 0.010 %
Gain Error Drift
(1)
1.0 ppm/°C
Common-Mode Rejection at DC 100 dB
f
CM
= 60Hz, f
DATA
= 10Hz 130 dB
f
CM
= 50Hz, f
DATA
= 50Hz 120 dB
f
CM
= 60Hz, f
DATA
= 60Hz 120 dB
Normal-Mode Rejection f
SIG
= 50Hz, f
DATA
= 50Hz 100 dB
f
SIG
= 60Hz, f
DATA
= 60Hz 100 dB
Output Noise See Typical Characteristics
Power-Supply Rejection at DC, dB = –20 log( ∆ V
OUT
/ ∆ V
DD
)
(2)
75 90 dB
VOLTAGE REFERENCE INPUT
Reference Input Range REF IN+, REF IN– 0 AV
DD
V
V
REF
V
REF
≡ (REF IN+) – (REF IN–) 0.1 1.25 V
Common-Mode Rejection at DC 120 dB
Common-Mode Rejection f
VREFCM
= 60Hz, f
DATA
= 60Hz 120 dB
Bias Current
(3)
V
REF
= 1.25V 0.65 µA
(1) Calibration can minimize these errors.
(2) ∆ V
OUT
is change in digital result.
(3) 12pF switched capacitor at f
SAMP
clock frequency.
5