Datasheet

www.ti.com
DEFINITION OF RULES
ENOB 
−20 log
(
ppm
)
6.02

2V
REF
PGA

10

6.02ER
20


V
REF
PGA

10

6.02ER
20

f
DATA


f
MOD
Decimation Ratio



f
OSC
mfactor  Decimation Ratio

f
SAMP

f
OSC
mfactor
f
SAMP

2f
OSC
mfactor
f
SAMP

8f
OSC
mfactor
f
SAMP

16f
OSC
mfactor
f
SAMP

16f
OSC
mfactor
ADS1218
SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005
The data from the A/D converter is output as codes,
which then can be easily converted to other units,
such as ppm or volts. The equations and table below
Analog Input Voltage—the voltage at any one
show the relationship between bits or codes, ppm,
analog input relative to AGND.
and volts.
Analog Input Differential Voltage—given by the
following equation: (A
IN+
) – (A
IN–
). Thus, a positive
digital output is produced whenever the analog input
differential voltage is positive, while a negative digital
BITS rms BIPOLAR Vrms UNIPOLAR Vrms
output is produced whenever the differential is
negative.
For example, when the converter is configured with a
2.5V reference and placed in a gain setting of 1, the
24 298nV 149nV
positive full-scale output is produced when the analog
22 1.19 µ V 597nV
input differential is 2.5V. The negative full-scale
output is produced when the differential is –2.5V. In
20 4.77 µ V 2.39 µ V
each case, the actual input voltages must remain
18 19.1 µ V 9.55 µ V
within the AGND to AV
DD
range.
16 76.4 µ V 38.2 µ V
Conversion Cycle—the term conversion cycle
14 505 µ V 152.7 µ V
usually refers to a discrete A/D conversion operation,
12 1.22mV 610 µ V
such as that performed by a successive
approximation converter. As used here, a conversion
f
DATA
—the frequency of the digital output data
cycle refers to the t
DATA
time period. However, each
produced by the ADS1218. f
DATA
is also referred to as
digital output is actually based on the modulator
the Data Rate.
results from several t
DATA
time periods.
FILTER SETTING MODULATOR RESULTS
Fast Settling 1 t
DATA
Time Period
Sinc
2
2 t
DATA
Time Period
f
MOD
—the frequency or speed at which the modulator
Sinc
3
3 t
DATA
Time Period
of the ADS1218 is running. This depends on the
SPEED bit as shown below:
Data Rate—the rate at which conversions are
SPEED BIT f
MOD
completed. See definition for f
DATA
.
0 f
OSC
/128
Decimation Ratio—defines the ratio between the
1 f
OSC
/256
output of the modulator and the output Data Rate.
Valid values for the Decimation Ratio are from 20 to
f
OSC
—the frequency of the crystal input signal at the
2047. Larger Decimation Ratios will have lower noise.
X
IN
input of the ADS1218.
Effective Resolution—the effective resolution of the
f
SAMP
—the frequency, or switching speed, of the input
ADS1218 in a particular configuration can be
sampling capacitor. The value is given by one of the
expressed in two different units: bits rms (referenced
following equations:
to output) and Vrms (referenced to input). Computed
directly from the converter’s output data, each is a
PGA SETTING SAMPLING FREQUENCY
statistical calculation. The conversion from one to the
1, 2, 4, 8
other is shown below.
Effective number of bits (ENOB) or effective
8
resolution is commonly used to define the usable
resolution of the A/D converter. It is calculated from
empirical data taken directly from the device. It is
16
typically determined by applying a fixed known signal
source to the analog input and computing the
32
standard deviation of the data sample set. The rms
noise defines the ± σ interval about the sample mean.
64, 128
37