Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- ELECTRICAL CHARACTERISTICS: AVDD = 5V
- ELECTRICAL CHARACTERISTICS: AVDD = 3V
- DIGITAL CHARACTERISTICS: TMIN to TMAX, DVDD = 2.7V to 5.25V
- FLASH CHARACTERISTICS: TMIN to TMAX, DVDD = 2.7V to 5.25V, unless otherwise specified.
- PIN CONFIGURATION
- TIMING SPECIFICATIONS
- TIMING SPECIFICATION TABLE
- TIMING SPECIFICATION TABLE
- TYPICAL CHARACTERISTICS
- OVERVIEW
- INPUT MULTIPLEXER
- TEMPERATURE SENSOR
- BURNOUT CURRENT SOURCES
- INPUT BUFFER
- IDAC1 AND IDAC2
- PGA
- PGA OFFSET DAC
- MODULATOR
- VOLTAGE REFERENCE INPUT
- ON-CHIP VOLTAGE REFERENCE
- VRCAP PIN
- CLOCK GENERATOR
- CALIBRATION
- DIGITAL FILTER
- DIGITAL I/O INTERFACE
- SERIAL PERIPHERAL INTERFACE
- DATA READY
- DSYNC OPERATION
- MEMORY
- REGISTER BANK
- RAM
- FLASH
- REGISTER MAP
- COMMAND DEFINITIONS
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D
IN
1111 1011
D
IN
1111 1110
ADS1218
SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005
WAKEUP Wakeup From Sleep Mode
Description: Use this command to wake up from sleep mode.
Operands: None
Bytes: 1
Encoding: 1111 1011
Data Transfer Sequence:
RESET Reset Registers
Description: Copy the contents of Flash memory page 0 to the registers. This command will also stop the Read
Continuous mode.
Operands: None
Bytes: 1
Encoding: 1111 1110
Data Transfer Sequence:
Table 4. ADS1218 Command Map
LSB
MSB 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
0000 x
(1)
rdata x rdatac x x x x x x x x x x x stopc
0001 rreg 0 rreg 1 rreg 2 rreg 3 rreg 4 rreg 5 rreg 6 rreg 7 rreg 8 rreg 9 rreg A rreg B rreg C rreg D rreg E rreg F
0010 rram 0 rram 1 rram 2 rram 3 rram 4 rram 5 rram 6 rram 7 x x x x x x x x
0011 x x x x x x x x x x x x x x x x
0100 creg 0 creg 1 creg 2 creg 3 creg 4 creg 5 creg 6 creg 7 crega x x x x x x x
0101 wreg 0 wreg 1 wreg 2 wreg 3 wreg 4 wreg 5 wreg 6 wreg 7 wreg 8 wreg 9 wreg A wreg B wreg C wreg D wreg E wreg F
0110 wram 0 wram 1 wram 2 wram 3 wram 4 wram 5 wram 6 wram 7 x x x x x x x x
0111 x x x x x x x x x x x x x x x x
1000 rf2r 0 rf2r 1 rf2r 2 rf2r 3 rf2r 4 rf2r 5 rf2r 6 rf2r 7 rf2r 8 rf2r 9 rf2r A rf2r B rf2r C rf2r D rf2r E rf2r F
1001 rf2r 10 rf2r 11 rf2r 12 rf2r 13 rf2r 14 rf2r 15 rf2r 16 rf2r 17 rf2r 18 rf2r 19 rf2r 1A rf2r 1B rf2r 1C rf2r 1D rf2r 1E rf2r 1F
1010 wr2f 0 wr2f 1 wr2f 2 wr2f 3 wr2f 4 wr2f 5 wr2f 6 wr2f 7 wr2f 8 wr2f 9 wr2f A wr2f B wr2f C wr2f D wr2f E wr2f F
1011 wr2f 10 wr2f 11 wr2f 12 wr2f 13 wr2f 14 wr2f 15 wr2f 16 wr2f 17 wr2f 18 wr2f 19 wr2f wr2f wr2f wr2f wr2f wr2f 1F
1A 1B 1C 1D 1E
1100 cram 0 cram 1 cram 2 cram 3 cram 4 cram 5 cram 6 cram 7 x x x x x x x x
1101 csramx csramx csramx csramx csramx csramx csramx csramx csramx x x x x x x csreg
0 1 2 3 4 5 6 7
1110 csram csram csram2 csram csram csram csram csram csramx x x x csfl x x x
0 1 3 4 5 6 7
1111 self cal self self sys sys x x x x x x x dsync sleep reset x
ocal gcal ocal gcal
(1) x = Reserved
36