Datasheet

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Offset 
V
REF
2PGA


Code
127

ADS1218
SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005
IDAC1 (Address 03
H
) Current DAC 1
Reset value is set by Flash memory page 0. Factory programmed to 00
H
.
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
IDAC1_7 IDAC1_6 IDAC1_5 IDAC1_4 IDAC1_3 IDAC1_2 IDAC1_1 IDAC1_0
The DAC code bits set the output of DAC1 from 0 to full-scale. The value of the full-scale current is set by this Byte, V
REF
, R
DAC
, and the
DAC1 range bits in the ACR register.
IDAC2 (Address 04
H
) Current DAC 2
Reset value is set by Flash memory page 0. Factory programmed to 00
H
.
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
IDAC2_7 IDAC2_6 IDAC2_5 IDAC2_4 IDAC2_3 IDAC2_2 IDAC2_1 IDAC2_0
The DAC code bits set the output of DAC2 from 0 to full-scale. The value of the full-scale current is set by this Byte, V
REF
, R
DAC
, and the
DAC2 range bits in the ACR register.
ODAC (Address 05
H
) Offset DAC Setting
Reset value is set by Flash memory page 0. Factory programmed to 00
H
.
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SIGN OSET6 OSET5 OSET4 OSET3 OSET2 OSET1 OSET0
bit 7 Offset Sign
0 = Positive
1 = Negative
bits 6-0
NOTE: The offset must be used after calibration or the calibration will notify the effects.
DIO (Address 06
H
) Digital I/O
Reset value is set by Flash memory page 0. Factory programmed to 00
H
.
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 DIO0
A value written to this register will appear on the digital I/O pins if the pin is configured as an output in the DIR register. Reading this
register will return the value of the digital I/O pins.
DIR (Address 07
H
) Direction control for digital I/O
Reset value is set by Flash memory page 0. Factory programmed to FF
H
.
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0
Each bit controls whether the Digital I/O pin is an output (= 0) or input (= 1). The default power-up state is as
inputs.
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