Datasheet

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FLASH
ADS1218
SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005
The RAM provides eight banks, with a bank The ADS1218 supports any combination of eight
consisting of 16 bytes. The total size of the RAM is analog inputs and the Flash memory supports up to
128 bytes. Copies between the registers and RAM 32 unique Page configurations. With this flexibility,
are performed on a bank basis. Also, the RAM can the device could support 32 unique configurations for
be directly read or written through the serial interface each of the eight analog input channels. For instance,
on power-up. The banks allow separate storage of the on-chip temperature sensor could be used to
settings for each input. monitor temperature, then different calibration
coefficients could be recalled for each of the eight
The RAM address space is linear; therefore,
analog input channels based on the change in
accessing RAM is done using an auto-incrementing
temperature. This would enable the user to recall
pointer. Access to RAM in the entire memory map
calibration coefficients for every 4°C change in
can be done consecutively without having to address
temperature over the industrial temperature range,
each bank individually. For example, if you were
which could be used to correct for drift errors.
currently accessing bank 0 at offset 0xF (the last
Checksum commands are also included, which can
location of bank 0), the next access would be bank 1
be used to verify the integrity of Flash.
and offset 0x0. Any access after bank 7 and offset
0xF will wrap around to bank 0 and Offset 0x0. The following two commands can be used to
manipulate the Flash. First, the contents of Flash can
Although the Register Bank memory is linear, the
be written to with the WR2F (write RAM to Flash)
concept of addressing the device can also be thought
command. This command first erases the designated
of in terms of bank and offset addressing. Looking at
Flash page and then writes the entire content of RAM
linear and bank addressing syntax, we have the
(all banks) into the designated Flash page. Second,
following comparison: in the linear memory map, the
the contents of Flash can be read with the RF2R
address 0x14 is equivalent to bank 1 and offset 0x4.
(read Flash to RAM) command. This command reads
Simply stated, the most significant four bits represent
the designated Flash page into the entire contents of
the bank, and the least significant four bits represent
RAM (all banks). In order to ensure maximum
the offset. The offset is equivalent to the register
endurance and data retention, the SPEED bit in the
address for that bank of memory.
SETUP register must be set for the appropriate f
OSC
frequency.
Writing to or erasing Flash can be disabled either
Reads and Writes to Flash occur on a Page basis.
through the WREN pin or the WREN register bit. If
Therefore, the entire contents of RAM is used for
the WREN pin is low OR the WREN bit is cleared,
both Read and Write operations. The Flash is
then the WR2F command has no effect. This protects
independent of the Registers; for example, the Flash
the integrity of the Flash data from being
can be used as general-purpose Flash.
inadvertently corrupted.
Upon power-up or reset, the contents of Flash Page 0
Accessing the Flash data either through read, write,
are loaded into RAM. Subsequently, the contents of
or erase may affect the accuracy of the conversion
RAM Bank 0 are loaded into the configuration
result. Therefore, the conversion result should be
register. Therefore, the user can customize the
discarded when accesses to Flash are done.
power-up configuration for the device. Care should be
taken to ensure that data for Flash Page 0 is written
correctly, in order to prevent unexpected operation
upon power-up.
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