Datasheet

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Serial Clock (SCLK)
REGISTER BANK
Polarity (POL)
DATA READY
DSYNC OPERATION
Configuration
Register Bank
16 bytes
SETUP
MUX
ACR
IDAC1
IDAC2
ODAC
DIO
DIR
DEC0
M/DEC1
OCR0
OCR1
OCR2
FSR0
FSR1
FSR2
RAM
128 Bytes
Bank 2
16 bytes
Bank 7
16 bytes
Bank 0
16 bytes
FLASH
4k Bytes
Page 0
128 bytes
Page 31
128 bytes
MEMORY
RAM
ADS1218
SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005
SCLK, a Schmitt Trigger input, clocks data transfer
The operation of the device is set up through
on the D
IN
input and D
OUT
output. When transferring
individual registers. The set of the 16 registers
data to or from the ADS1218, multiple bits of data
required to configure the device is referred to as a
may be transferred back-to-back with no delay in
Register Bank, as shown in Figure 29 .
SCLKs or toggling of CS. Make sure to avoid glitches
on SCLK because they can cause extra shifting of the
data.
The serial clock polarity is specified by the POL input.
When SCLK is active high, set POL high. When
SCLK is active low, set POL low.
The DRDY output is used as a status signal to
indicate when data is ready to be read from the
ADS1218. DRDY goes low when new data is
available. It is reset high when a read operation from
the data register is complete. It also goes high prior
to the updating of the output register to indicate when
not to read from the device to ensure that a data read
is not attempted while the register is being updated.
DSYNC is used to provide for synchronization of the
A/D conversion with an external event.
Synchronization can be achieved either through the
DSYNC pin or the DSYNC command. When the
DSYNC pin is used, the filter counter is reset on the
falling edge of DSYNC. The modulator is held in reset
until DSYNC is taken high. Synchronization occurs on
the next rising edge of the system clock after DSYNC
is taken high.
Figure 29. Memory Organization
Three types of memory are used on the ADS1218:
registers, RAM, and Flash. 16 registers directly
control the various functions (PGA, DAC value,
Decimation Ratio, etc.) and can be directly read or
written to. Collectively, the registers contain all the
Reads and Writes to Registers and RAM occur on a
information needed to configure the part, such as
byte basis. However, copies between registers and
data format, mux settings, calibration settings,
RAM occurs on a bank basis. The RAM is
decimation ratio, etc. Additional registers, such as
independent of the Registers; for example, the RAM
conversion data, are accessed through dedicated
can be used as general-purpose RAM.
instructions.
The ADS1218 supports any combination of eight
The on-chip Flash can be used to store non-volatile
analog inputs. With this flexibility, the device could
data. The Flash data is separate from the
easily support eight unique configurations—one per
configuration registers and therefore can be used for
input channel. In order to facilitate this type of usage,
any purpose, in addition to device configuration. The
eight separate register banks are available.
Flash page data is read and written in 128 byte
Therefore, each configuration could be written once
blocks through the RAM banks; for example, all RAM
and recalled as needed without having to serially
banks map to a single page of Flash, as shown in
retransmit all the configuration data. Checksum
Figure 29 .
commands are also included, which can be used to
verify the integrity of RAM.
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