Datasheet

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PGA V
RCAP
PIN
CLOCK GENERATOR
PGA OFFSET DAC
MODULATOR
C
1
Crystal
X
IN
X
OUT
C
2
VOLTAGE REFERENCE INPUT
CALIBRATION
ON-CHIP VOLTAGE REFERENCE
ADS1218
SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005
The Programmable Gain Amplifier (PGA) can be set This pin provides a bypass cap for noise filtering on
to gains of 1, 2, 4, 8, 16, 32, 64, or 128. Using the internal V
REF
circuitry only. As this is a sensitive pin,
PGA can improve the effective resolution of the A/D place the capacitor as close as possible and avoid
converter. For instance, with a PGA of 1 on a 5V any resistive loading. The recommended capacitor is
full-scale range, the A/D converter can resolve to a 1000pF ceramic cap. If an external V
REF
is used,
1µV. With a PGA of 128, on a 40mV full-scale range, this pin can be left unconnected.
the A/D converter can resolve to 75nV.
The clock source for the ADS1218 can be provided
The input to the PGA can be shifted by half the from a crystal, oscillator, or external clock. When the
full-scale input range of the PGA by using the ODAC clock source is a crystal, external capacitors must be
register. The ODAC (Offset DAC) register is an 8-bit provided to ensure startup and a stable clock
value; the MSB is the sign and the seven LSBs frequency; see Figure 26 and Table 1 .
provide the magnitude of the offset. Using the ODAC
register does not reduce the performance of the A/D
converter. See Application Report The Offset DAC
(SBAA077 ) for more information.
The modulator is a single-loop second-order system.
The modulator runs at a clock speed (f
MOD
) that is
derived from the external clock (f
OSC
). The frequency
Figure 26. Crystal Connection
division is determined by the SPEED bit in the
SETUP register.
Table 1. Typical Clock Sources
SPEED BIT f
MOD
CLOCK FREQUENCY C
1
C
2
PART NUMBER
0 f
OSC
/128
SOURCE
1 f
OSC
/256
Crystal 2.4576 0-20pF 0-20pF ECS, ECSD 2.45 - 32
Crystal 4.9152 0-20pF 0-20pF ECS, ECSL 4.91
Crystal 4.9152 0-20pF 0-20pF ECS, ECSD 4.91
Crystal 4.9152 0-20pF 0-20pF CTS, MP 042 4M9182
The ADS1218 uses a differential voltage reference
input. The input signal is measured against the
differential voltage V
REF
≡ (V
REF+
) – (V
REF–
). For
AV
DD
= 5V, V
REF
is typically 2.5V. For AV
DD
= 3V,
The offset and gain errors in the ADS1218, or the
V
REF
is typically 1.25V. Due to the sampling nature of
complete system, can be reduced with calibration.
the modulator, the reference input current increases
Internal calibration of the ADS1218 is called self
with higher modulator clock frequency (f
MOD
) and
calibration. This is handled with three commands.
higher PGA settings.
One command does both offset and gain calibration.
There is also a gain calibration command and an
offset calibration command. Each calibration process
takes seven t
DATA
periods to complete. It takes 14
A selectable voltage reference (1.25V or 2.5V) is
t
DATA
periods to complete both an offset and gain
available for supplying the voltage reference input. To
calibration. Self-gain calibration is optimized for PGA
use, connect V
REF–
to AGND and V
REF+
to V
REFOUT
.
gains less than 8. When using higher gains, system
The enabling and voltage selection are controlled
gain calibration is recommended.
through bits REF EN and REF HI in the setup
register. The 2.5V reference requires AV
DD
= 5V.
For system calibration, the appropriate signal must be
When using the on-chip voltage reference, the
applied to the inputs. The system offset command
V
REFOUT
pin should be bypassed with a 0.1µF
requires a zero differential input signal. It then
capacitor to AGND.
computes an offset that will nullify offset in the
system. The system gain command requires a
positive full-scale differential input signal. It then
computes a value to nullify gain errors in the system.
Each of these calibrations will take seven t
DATA
periods to complete.
17