Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal TQFP 48

Table Of Contents

 

  

FEATURES

APPLICATIONS

DESCRIPTION

BUF PGA

1.25V or

2.5V

Reference

Clock Generator

Registers

Serial Interface

2nd−Order

Modulator

RAM

4K Bytes

FLASH

AGND AV

DAC

REFOUT

RCAP

REF+

REF

−

OUT

DSYNCPDWN RESET DRDYBUFENDGNDDV

WREN

Digital I/O

Interface

D7...D0

SCLK

POL

OUT

MUX

INCOM

IDAC1

Controller

Program−

mable

Digital

Filter

8−Bit

IDAC

IDAC2

8−Bit

IDAC

Offset

DAC

ADS1218

SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005

8-Channel, 24-Bit

ANALOG-TO-DIGITAL CONVERTER with FLASH Memory

The eight input channels are multiplexed. Internal

buffering can be selected to provide a very high input

• 24 BITS NO MISSING CODES

impedance for direct connection to transducers or

• 0.0015% INL

low-level voltage signals. Burnout current sources are

provided that allow for the detection of an open or

• 22 BITS EFFECTIVE RESOLUTION (PGA = 1),

shorted sensor. An 8-bit Digital-to-Analog (D/A)

19 BITS (PGA = 128)

converter provides an offset correction with a range

• 4K BYTES OF FLASH MEMORY

of 50% of the FSR (Full-Scale Range).

PROGRAMMABLE FROM 2.7V TO 5.25V

The PGA (Programmable Gain Amplifier) provides

• PGA FROM 1 TO 128

selectable gains of 1 to 128 with an effective

• SINGLE CYCLE SETTLING MODE

resolution of 19 bits at a gain of 128. The A/D

• PROGRAMMABLE DATA OUTPUT RATES UP

conversion is accomplished with a second-order

TO 1kHz

delta-sigma modulator and programmable sinc filter.

The reference input is differential and can be used for

• PRECISION ON-CHIP 1.25V/2.5V REFERENCE:

ratiometric conversion. The on-board current DACs

ACCURACY: 0.2%

(Digital-to-Analog Converters) operate independently

DRIFT: 5ppm/°C

with the maximum current set by an external resistor.

• EXTERNAL DIFFERENTIAL REFERENCE OF

The serial interface is SPI-compatible. Eight bits of

0.1V TO 2.5V

digital I/O are also provided that can be used for input

• ON-CHIP CALIBRATION

or output. The ADS1218 is designed for

• PIN-COMPATIBLE WITH ADS1216

high-resolution measurement applications in smart

transmitters, industrial process control, weight scales,

• SPI™ COMPATIBLE

chromatography, and portable instrumentation.

• 2.7V TO 5.25V

• < 1mW POWER CONSUMPTION

• INDUSTRIAL PROCESS CONTROL

• LIQUID/GAS CHROMATOGRAPHY

• BLOOD ANALYSIS

• SMART TRANSMITTERS

• PORTABLE INSTRUMENTATION

• WEIGHT SCALES

• PRESSURE TRANSDUCERS

The ADS1218 is a precision, wide dynamic range,

delta-sigma, Analog-to-Digital (A/D) converter with

24-bit resolution and Flash memory operating from

2.7V to 5.25V supplies. The delta-sigma, A/D

converter provides up to 24 bits of no missing code

performance and effective resolution of 22 bits.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SPI is a trademark of Motorola.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (44 pages)

PAGE 1
ADS1218 SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 8-Channel, 24-Bit ANALOG-TO-DIGITAL CONVERTER with FLASH Memory FEATURES • • • • • • • • • • • • • • 24 BITS NO MISSING CODES 0.0015% INL 22 BITS EFFECTIVE RESOLUTION (PGA = 1), 19 BITS (PGA = 128) 4K BYTES OF FLASH MEMORY PROGRAMMABLE FROM 2.7V TO 5.25V PGA FROM 1 TO 128 SINGLE CYCLE SETTLING MODE PROGRAMMABLE DATA OUTPUT RATES UP TO 1kHz PRECISION ON-CHIP 1.25V/2.5V REFERENCE: ACCURACY: 0.
PAGE 2
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
PAGE 3
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS: AVDD = 5V All specifications TMIN to TMAX, AVDD = +5V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, fOSC = 2.4576MHz, PGA = 1, Buffer On, RDAC = 150kΩ, VREF ≡ (REF IN+) – (REF IN–) = +2.5V, and fDATA = 10Hz, unless otherwise specified. ADS1218 PARAMETER CONDITIONS MIN TYP Buffer Off AGND – 0.1 Buffer On AGND + 0.05 MAX UNIT AVDD + 0.1 V AVDD – 1.
PAGE 4
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS: AVDD = 5V (continued) All specifications TMIN to TMAX, AVDD = +5V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, fOSC = 2.4576MHz, PGA = 1, Buffer On, RDAC = 150kΩ, VREF ≡ (REF IN+) – (REF IN–) = +2.5V, and fDATA = 10Hz, unless otherwise specified. ADS1218 PARAMETER CONDITIONS MIN TYP MAX UNIT REF HI = 1 at +25°C 2.495 2.50 2.
PAGE 5
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS: AVDD = 3V All specifications TMIN to TMAX, AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, fOSC = 2.4576MHz, PGA = 1, Buffer On, RDAC = 75kΩ, VREF ≡ (REF IN+) – (REF IN–) = +1.25V, and fDATA = 10Hz, unless otherwise specified. ADS1218 PARAMETER CONDITIONS MIN TYP Buffer Off AGND – 0.1 Buffer On AGND + 0.05 MAX UNIT AVDD + 0.1 V AVDD – 1.
PAGE 6
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS: AVDD = 3V (continued) All specifications TMIN to TMAX, AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, fOSC = 2.4576MHz, PGA = 1, Buffer On, RDAC = 75kΩ, VREF ≡ (REF IN+) – (REF IN–) = +1.25V, and fDATA = 10Hz, unless otherwise specified. ADS1218 PARAMETER CONDITIONS MIN TYP MAX REF HI = 0 at +25°C 1.245 1.25 1.
PAGE 7
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 DIGITAL CHARACTERISTICS: TMIN to TMAX, DVDD = 2.7V to 5.25V PARAMETER CONDITIONS MIN TYP MAX UNIT Digital Input/Output Logic Family CMOS Logic Level VIH 0.8 × DVDD DVDD V VIL DGND 0.2 × DVDD V VOH IOH = 1mA DVDD – 0.4 VOL IOL = 1mA DGND V DGND + 0.
PAGE 8
ADS1218 www.ti.
PAGE 9
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 TIMING SPECIFICATIONS CS t3 t1 t2 t10 SCLK (POL = 0) SCLK (POL = 1) t4 DIN MSB t2 t6 t5 t 11 LSB (Command or Command and Data) DOUT t7 t8 t9 MSB(1) LSB(1) NOTE: (1) Bit Order = 0.
PAGE 10
ADS1218 www.ti.
PAGE 11
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, VREF ≡ (REF IN+) – (REF IN–) = +2.5V, and fDATA = 10Hz, unless otherwise specified.
PAGE 12
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS (continued) AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, VREF ≡ (REF IN+) – (REF IN–) = +2.5V, and fDATA = 10Hz, unless otherwise specified.
PAGE 13
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS (continued) AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, VREF ≡ (REF IN+) – (REF IN–) = +2.5V, and fDATA = 10Hz, unless otherwise specified. GAIN vs TEMPERATURE INTEGRAL NONLINEARITY vs INPUT SIGNAL 1.00010 10 8 1.00002 0.99998 0.99994 4 +85 C 2 0 −2 −4 +25 C −6 0.99990 0.99986 − 40 C 6 INL (ppm of FS) Gain (Normalized) 1.00006 −8 −50 −30 −10 10 30 50 70 −10 −2.
PAGE 14
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS (continued) AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, VREF ≡ (REF IN+) – (REF IN–) = +2.5V, and fDATA = 10Hz, unless otherwise specified. VREFOUT vs LOAD CURRENT OFFSET DAC – OFFSET vs TEMPERATURE 2.55 200 170 Offset (ppm of FSR) VREFOUT (V) 140 2.50 110 80 50 20 −10 −40 −70 2.45 −0.5 −100 0 0.5 1.0 1.5 2.0 2.
PAGE 15
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS (continued) AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, VREF ≡ (REF IN+) – (REF IN–) = +2.5V, and fDATA = 10Hz, unless otherwise specified. IDAC INTEGRAL NONLINEARITY RANGE = 1, RDAC = 150kΩ, VREF = 2.5V 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 INL (LSB) DNL (LSB) IDAC DIFFERENTIAL NONLINEARITY RANGE = 1, RDAC = 150kΩ, VREF = 2.5V 0.1 0 −0.1 0.1 0 −0.1 −0.2 −0.2 −0.3 −0.3 −0.4 −0.
PAGE 16
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 OVERVIEW INPUT MULTIPLEXER The input multiplexer provides for any combination of differential inputs to be selected on any of the input channels, as shown in Figure 25. For example, if channel 1 is selected as the positive differential input channel, any other channel can be selected as the negative differential input channel. With this method, it is possible to have up to eight fully differential input channels.
PAGE 17
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 PGA VRCAP PIN The Programmable Gain Amplifier (PGA) can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128. Using the PGA can improve the effective resolution of the A/D converter. For instance, with a PGA of 1 on a 5V full-scale range, the A/D converter can resolve to 1µV. With a PGA of 128, on a 40mV full-scale range, the A/D converter can resolve to 75nV.
PAGE 18
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 Calibration must be performed after power on, a change in decimation ratio, or a change of the PGA. For operation with a reference voltage greater than (AVDD– 1.5V), the buffer must also be turned off during calibration. At the completion of calibration, the DRDY signal goes low, which indicates the calibration is finished and valid data is available.
PAGE 19
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 SINC2 FILTER RESPONSE(1) (−3dB = 0.318 • f DATA = 19.11Hz) 0 0 −20 −20 −40 −40 Gain (dB) Gain (dB) SINC3 FILTER RESPONSE(1) (−3dB = 0.262 • fDATA = 15.76Hz) −60 −80 −60 −80 −100 −100 −120 −120 0 30 60 90 120 150 180 210 240 270 300 0 30 60 90 Frequency (Hz) 120 150 180 210 240 270 300 Frequency (Hz) FAST SETTLING FILTER RESPONSE(1) (−3dB = 0.469 • fDATA = 28.
PAGE 20
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 Serial Clock (SCLK) REGISTER BANK SCLK, a Schmitt Trigger input, clocks data transfer on the DIN input and DOUT output. When transferring data to or from the ADS1218, multiple bits of data may be transferred back-to-back with no delay in SCLKs or toggling of CS. Make sure to avoid glitches on SCLK because they can cause extra shifting of the data. The operation of the device is set up through individual registers.
PAGE 21
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 The RAM provides eight banks, with a bank consisting of 16 bytes. The total size of the RAM is 128 bytes. Copies between the registers and RAM are performed on a bank basis. Also, the RAM can be directly read or written through the serial interface on power-up. The banks allow separate storage of settings for each input. The RAM address space is linear; therefore, accessing RAM is done using an auto-incrementing pointer.
PAGE 22
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 REGISTER MAP Table 2.
PAGE 23
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 MUX (Address 01H) Multiplexer Control Register Reset value is set by Flash memory page 0. Factory programmed to 01H.
PAGE 24
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 IDAC1 (Address 03H) Current DAC 1 Reset value is set by Flash memory page 0. Factory programmed to 00H. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 IDAC1_7 IDAC1_6 IDAC1_5 IDAC1_4 IDAC1_3 IDAC1_2 IDAC1_1 IDAC1_0 The DAC code bits set the output of DAC1 from 0 to full-scale. The value of the full-scale current is set by this Byte, VREF, RDAC, and the DAC1 range bits in the ACR register.
PAGE 25
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 DEC0 (Address 08H) Decimation Register (least significant 8 bits) Reset value is set by Flash memory page 0. Factory programmed to 80H. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DEC07 DEC06 DEC05 DEC04 DEC03 DEC02 DEC01 DEC00 The decimation value is defined with 11 bits for a range of 20 to 2047. This register is the least significant 8 bits. The 3 most significant bits are contained in the M/DEC1 register.
PAGE 26
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 OCR1 (Address 0BH) Offset Calibration Coefficient (middle byte) Reset value is set by Flash memory page 0. Factory programmed to 00H. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 OCR15 OCR14 OCR13 OCR12 OCR11 OCR10 OCR09 OCR08 OCR2 (Address 0CH) Offset Calibration Coefficient (most significant byte) Reset value is set by Flash memory page 0. Factory programmed to 00H.
PAGE 27
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 COMMAND DEFINITIONS The commands listed below control the operation of the ADS1218. Some of the commands are stand-alone commands (e.g., RESET) while others require additional bytes (e.g., WREG requires command, count, and the data bytes). Commands that output data require a minimum of four fOSC cycles before the data is ready (e.g., RDATA).
PAGE 28
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 RDATA Read Data Description: Read a single 24-bit ADC conversion result. On completion of read back, DRDY goes high. Operands: None Bytes: 1 Encoding: 0000 0001 Data Transfer Sequence: DRDY • • • (1) 0000 0001 DIN DOUT xxxx xxxx xxxx xxxx xxxx xxxx MSB Mid−Byte LSB RDATAC Read Data Continuous Description: Read Data Continuous mode enables the continuous output of new data on each DRDY.
PAGE 29
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 STOPC Stop Continuous Description: Ends the continuous data output mode. Operands: None Bytes: 1 Encoding: 0000 1111 Data Transfer Sequence: DIN 0000 1111 RREG Read from Registers Description: Output the data from up to 16 registers starting with the register address specified as part of the instruction. The number of registers read will be one plus the second byte.
PAGE 30
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 CREG Copy Registers to RAM Bank Description: Copy the 16 control registers to the RAM bank specified in the op code. Refer to timing specifications for command execution time. Operands: a Bytes: 1 Encoding: 0100 0aaa Data Transfer Sequence: Copy Register Values to RAM Bank 3 DIN 1101 1111 • • • (1) xxxx xxxx Checksum DOUT NOTE: (1) For wait time, refer to timing specification.
PAGE 31
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 WRAM Write to RAM Description: Write up to 128 RAM locations starting at the beginning of the RAM bank specified as part of the instruction. The number of bytes written is RAM is one plus the value of the second byte.
PAGE 32
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 CRAM Copy RAM Bank to Registers Description: Copy the selected RAM Bank to the Configuration Registers. This will overwrite all of the registers with the data from the RAM bank. Operands: a Bytes: 1 Encoding: 1100 0aaa Data Transfer Sequence: Copy RAM Bank 0 to the Registers DIN 1100 0000 CSRAMX Calculate RAM Bank Checksum Description: Calculate the checksum of the selected RAM Bank.
PAGE 33
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 CSREG Calculate the Checksum of Registers Description: Calculate the checksum of all the registers. The checksum is calculated as a sum of all the bytes with the carry ignored. The ID, DRDY, and DIO bits are masked so they are not included in the checksum. Operands: None Bytes: 1 Encoding: 1101 1111 Data Transfer Sequence: DIN 1101 1111 • • • (1) xxxx xxxx Checksum DOUT NOTE: (1) For wait time, refer to timing specification.
PAGE 34
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 CSFL Calculate Checksum for all Flash Memory Pages Description: Calculate the checksum for all Flash memory pages. The checksum is calculated as a sum of all the bytes with the carry ignored. All bits are included in the checksum calculation; there is no masking of bits.
PAGE 35
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 SYSOCAL System Offset Calibration Description: Starts the system offset calibration process. For a system offset calibration, the input should be set to 0V differential, and the ADS1218 computes the OCR register value that will compensate for offset errors. The Offset Control Register (OCR) is updated after this operation.
PAGE 36
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 WAKEUP Wakeup From Sleep Mode Description: Use this command to wake up from sleep mode. Operands: None Bytes: 1 Encoding: 1111 1011 Data Transfer Sequence: DIN 1111 1011 RESET Reset Registers Description: Copy the contents of Flash memory page 0 to the registers. This command will also stop the Read Continuous mode. Operands: None Bytes: 1 Encoding: 1111 1110 Data Transfer Sequence: DIN 1111 1110 Table 4.
PAGE 37
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 DEFINITION OF RULES Analog Input Voltage—the voltage at any one analog input relative to AGND. Analog Input Differential Voltage—given by the following equation: (AIN+) – (AIN–). Thus, a positive digital output is produced whenever the analog input differential voltage is positive, while a negative digital output is produced whenever the differential is negative.
PAGE 38
ADS1218 www.ti.com SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 Filter Selection—the ADS1218 uses a (sinx/x) filter or sinc filter. There are three different sinc filters that can be selected. A fast settling filter will settle in one tDATA cycle. The sinc2 filter will settle in two cycles and have lower noise. The sinc3 will achieve lowest noise and higher number of effective bits, but requires three cycles to settle.
PAGE 39
PACKAGE OPTION ADDENDUM www.ti.
PAGE 40
PACKAGE MATERIALS INFORMATION www.ti.com 12-Dec-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS1218Y/250 Package Package Pins Type Drawing TQFP PFB 48 SPQ 250 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 177.8 16.4 Pack Materials-Page 1 9.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.6 1.5 12.0 16.
PAGE 41
PACKAGE MATERIALS INFORMATION www.ti.com 12-Dec-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1218Y/250 TQFP PFB 48 250 210.0 185.0 35.
PAGE 42
MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
PAGE 43
PAGE 44
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.